Ferroelectric transistor and memory cell configuration with the ferroelectric transistor

A ferroelectric transistor, comprising:

• a substrate having a main surface;
• a first source-drain region, a channel region, and a second source-drain region adjoining said main surface of said semiconductor substrate, with said channel region arranged between said first and second source-drain regions;
• a dielectric layer covering at least said channel region and overlapping said first source-drain region;
• a ferroelectric layer disposed on said dielectric layer and covering at least a part of said first source-drain region adjacent said channel region;
• a first polarization electrode and a second polarization electrode disposed on said dielectric layer, with said ferroelectric layer arranged between said first and second polarization electrodes;
• a gate electrode above a first area of said channel region;
• said dielectric layer having a thickness above said first area less than a thickness above a second area of said channel region below said second polarization electrode;
• and
• said dielectric layer having a thickness above said part of said first source-drain region adjoining said channel region dimensioned such that a remanent polarization of said ferroelectric layer, aligned parallel to said main surface of said substrate, produces compensation charges in said second area of said channel region.