Field effect transistor and image display apparatus using the same
AssigneeHitachi, Ltd.
InventorHajime Akimoto
Life of this patent
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Abstract
A field effect transistor includes an n+ high-density impurity injection area, a p+ high-density impurity injection area, an i-impurity non-injection area, and a gate electrode. The gate electrode is free from completely lapping over the i-impurity non-injection area, but laps over substantially half the i-impurity non-injection area adjacent to the n+ high-density impurity injection area so as to avoid channel carrier capture levels due to crystal defects/grain boundaries and an effect of potential barriers due to the channel carrier capture levels.
Claims16
An insulated gate field effect transistor having a gate electrode in a channel area between a first and second types of source areas thereof, wherein:
- said channel area comprises an area portion free from lapping over the gate electrode in plan.
An insulated gate type field effect transistor having a gate electrode in a channel area between a first and a second types of source areas thereof, wherein:
- said gate electrode comprises two separate subgate electrodes disposed on the respective sides of said first and second types of source areas in a direction in which said channel area extends.
A double field effect transistor device of an insulated gate type, comprising:
- a channel area taking a virtually H-type form in plan;
- a first pair of source areas different in conductive type respectively formed at opposite ends of one of a pair of parallel strips that composes a part of the H;
- a second pair of source areas different in conductive type respectively formed at opposite ends of the other of said pair of parallel strips that composes a part of the H so that the source areas formed respectively at the ends of said pair of parallel strips extending in the same direction are different in conductive type;
- and
- a gate electrode lapping over an area of the H that comprises the central portions of said pair of parallel strips that composes a part of the H and a central link of the H that combines said pair of parallel strips.
An image display apparatus comprising a display unit of a plurality of pixels formed on an insulating substrate, and a controller formed on the insulating substrate for at least processing a display signal and for writing the display signal to said display unit, wherein.
- at least part of said controller is of an insulated gate type having a gate electrode in a channel area between a first and second types of source areas thereof;
- and
- said channel area comprises an area portion free from lapping over the gate electrode in plan.
An image display apparatus comprising a display unit of a plurality of pixels formed on an insulating substrate, and a controller formed on the insulating substrate for at least processing a display signal and for writing the display signal to said display unit, wherein.
- at least part of said controller is of an insulated gate type having a gate electrode in a channel area between a first and second source areas thereof;
- and
- said channel area comprises an area portion free from lapping over the gate electrode in plan;
- and said apparatus comprising:
- an image control unit of said display unit being of an insulated gate type, said image control unit comprising:
- a channel area taking a virtually H-type form;
- a first pair of source areas different in conductive type respectively formed at opposite ends of one of a pair of parallel strips that composes a part of the H;
- a second pair of source areas different in conductive type respectively formed at opposite ends of the other of said pair of parallel strips that composes a part of the H so that the source areas formed respectively at the ends of said pair of parallel strips extending in the same direction are different in conductive type;
- and
- a gate electrode lapping over an area of the H that comprises the central portions of said pair of parallel strips that composes a part of the H and a central link of the H that combines said pair of parallel strips.
Dependencies are inferred from the claim text.