Semiconductor device wiring and method of manufacturing the same

A wiring of a semiconductor device comprising:

• a first conductive layer formed on a semiconductor substrate;
• first insulation layer formed on said first conductive layer, planarized by a CMP process and having a scratch on a surface thereof;
• a second insulation layer formed on said first insulation layer and having a groove formed therein;
• and
• a second conductive layer formed in said groove, having a thickness thinner than a thickness of said second insulation layer.

A method of manufacturing a wiring of a semiconductor device comprising the steps of:

• forming a first conductive layer on a semiconductor substrate;
• forming a first insulation layer on said conductive layer by depositing a first insulating material and implementing a CMP process;
• forming a second insulation layer by depositing a second insulation material on said first insulation layer in order to cover a scratch formed on said first insulation layer after implementing said CMP process;
• forming an etching pattern by etching said second insulation layer to a thickness less than a thickness of said second insulation layer;
• and
• forming a conductive pattern of a second conductive layer having a damascene shape by depositing a conductive material on said etching pattern and then planarizing the second conductive layer.