Adaptive dirty-block purging
AssigneeCompaq Computer Corporation
InventorsSimon C. Steely JR., Nikolaos Hardavellas
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AssigneeCompaq Computer Corporation
InventorsSimon C. Steely JR., Nikolaos Hardavellas
Estimating the term…
An adaptive cache coherent purging protocol includes recognizing system performance, especially latency, is affected by when cache is purged. The occurrence of performance enhancing and degrading events regarding a cache are counted and compared to a threshold. When the threshold is triggered the cache becomes a candidate for purging. In an embodiment, a time out delay is implemented before actual purging occurs. When the threshold is not triggered but a cache event occurs, a fake time out delay is triggered and the count is adaptively either raised, lowered or set to zero in response to performance enhancing and/or degrading events. The effect is to make the actual purging more likely if the history of cache events indicates that the performance would be enhanced thereby or less likely if the history indicates that the performance would be degraded thereby.
A method for adaptively determining cache data candidates for purging, wherein physical cache memory is associated with a local component of a local node in a modular multiprocessor system having a of plurality interconnected processors, I/O ports, and memory, the method comprising the steps of:
A system for adaptively determining cache data candidates for purging, wherein physical cache memory is associated with a local component of a local node in a modular multiprocessor system having a plurality of interconnected processors, I/O ports, and memory, the system comprising:
Dependencies are inferred from the claim text.