Full-speed bist controller for testing embedded synchronous memories

A method for testing embedded synchronous memory in an integrated circuit, the method comprising:

• generating an expected data value;
• pipelining the generated expected data value to delay the expected data value at least one clock cycle;
• reading an actual data value from the memory;
• and
• comparing the actual data value to the pipelined expected data value using compare circuitry.

A method for testing embedded memory, comprising:

• (a) during a first clock cycle, setting up an address register for a first read of memory;
• (b) during a second clock cycle, completing the first read and comparing the data read to an expected data value;
• (c) during the second clock cycle, setting up the address register for a second read or a write;
• (d) during a third clock cycle, providing an output for the first read indicating whether the first read past or failed based on whether the data read matched the expected data value;
• and
• (e) during the third clock cycle, completing the second read or the write.

A method for testing embedded synchronous memory in an integrated circuit, the method comprising:

• (a) selectively configuring the integrated circuit into a test mode for testing the memory;
• (b) using a BIST controller, loading an address of the memory location to be tested;
• (c) using the BIST controller, generating an expected data value that represents the correct data associated with the memory address;
• (d) using the BIST controller, providing control signals to or loading a compare capture circuit used to control compare circuitry;
• (e) reading the actual data value from the memory, the data value stored in memory at the memory address generated by the BIST controller;
• (f) comparing the actual data value from the memory with the expected data value from the BIST controller;
• and
• (g) pipelining at least the compare capture circuit so that the BIST controller can perform consecutive reads and compares every clock cycle of the memory.