Information processor and information processing system utilizing interface for synchronizing clock signal

A data processing apparatus coupled to a memory via a data bus, and integrated on a single semiconductor substrate, comprising:

• a clock generator, coupled to an oscillator, including a phase lock loop circuit;
• and
• a logic device coupled to said bus and clock generator,
• wherein said clock generator receives a first clock signal from the oscillator, and generates a second clock signal whose frequency is a multiple of said first clock signal, and
• wherein said logic device receives said second clock signal from said clock generator, and loads data from the memory.

A data processing apparatus integrated on a single semiconductor substrates, comprising:

• a clock generator;
• and
• a logic device couple to said a clock generator,
• wherein said clock generator comprises:
• a phase comparator coupled to a first clock signal having a first frequency,
• a low pass filter coupled to said phase comparator,
• a voltage controlled oscillator coupled to said low pass filter,
• a frequency divider coupled to said voltage controlled oscillator, and
• a feedback path coupled between said frequency divider and said phase comparator,
• wherein said clock generator produces a second clock signal whose frequency is a multiple of said first frequency, and
• wherein said logic device receives said second clock signal from said clock generator and subjects input data to a logical operation.