Activation of word lines in semiconductor memory device

A semiconductor memory device comprising:

• a plurality of memory cell blocks composed of dynamic memory cells arranged in a matrix, the memory cell block including a plurality of word lines;
• an address input section for input of a multiple-bit address that includes a block address for selecting any one block from among the plurality of memory cell blocks, and a row address for selecting one of the plurality of word lines in the selected memory cell block;
• a data input/output section for input/output of data corresponding to a memory cell selected by the multiple-bit address;
• and
• a word line activation controller for controlling activation of the word lines;
• wherein the word line activation controller comprises:
• a row address transition detector for detecting whether the row address has changed;
• and wherein the word line activation controller is capable of:
• (a) in a first case that the row address transition detector does not detect a change in the row address during consecutive cycles in which read or write operations of data for the memory cells are enabled and in which an identical row address is used, maintaining an activated state of a word line activated in a first memory cell block during an initial cycle of the consecutive cycles, without deactivation thereof until a final cycle of the consecutive cycles;
• (b) in a second case that a refresh request is issued to perform a refresh operation on the first memory cell block while the activated word line in the first memory cell block is maintained in the activated state, deactivating the activated word line in the first memory cell block if no read or write operations of data are currently being performed in the first memory cell block;
• and
• (c) in a third case that a read or write operation for the first memory cell block is requested within a predetermined period after the issuance of the refresh request to the first memory cell block, suspending the refresh operation for the first memory cell block, and activating the deactivated word line in the first memory cell block for the read or write operation of data.