Circuit configuration for enhancing performance characteristics of fabricated devices

A combination, comprising:

• at least three devices connected in series, said devices of a type that produce an output signal that transitions between different states;
• an n-channel device connected to provide resistance to a high-to-low transition;
• and
• a p-channel device connected to provide resistance to a low-to high transition.

A memory device, comprising:

• an array of memory cells;
• an address decoder for receiving an address and for identifying at least a specific cell in said array of memory cells corresponding to said address;
• a read/write circuit for reading information out of and writing information into said specific cell;
• a control logic circuit for receiving command signals and generating control signals in response thereto for controlling said address decoder and said read/write circuit;
• and
• a clock circuit for producing clocking signals for input to said control logic, said clock circuit including a path for delaying the clock signal comprising:
• at least three inverters connected in series;
• an n-channel device connected at an output of one of said inverters to provide resistance to a high-to-low transition;
• and
• a p-channel device connected at an output of one of said inverters to provide resistance to a low-to high transition.

A memory device, comprising:

• an array of memory cells;
• an address decoder for receiving an address and for identifying at least a specific cell in said array of memory cells corresponding to said address;
• a read/write circuit for reading information out of and writing information into said specific cell;
• a control logic circuit for receiving command signals and generating control signals in response thereto for controlling said address decoder and said read/write circuit;
• and
• a clock circuit for producing clocking signals for input to said control logic, said clock circuit including a path for delaying the clock signal comprising:
• at least three inverters connected in series;
• and
• at least one transistor connected to oppose a transition at the output of one of said inverters.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus;
• an output device coupled to the processor through the processor bus;
• and
• a memory device coupled to the processor bus, the memory device comprising:
• an array of memory cells;
• an address decoder for receiving an address and for identifying at least a specific cell in said array of memory cells corresponding to said address;
• a read/write circuit for reading information out of and writing information into said specific cell;
• a control logic circuit for receiving command signals and generating control signals in response thereto for controlling said address decoder and said read/write circuit;
• and
• a clock circuit for producing clocking signals for input to said control logic, said clock circuit including a path for delaying the clock signal comprising:
• at least three inverters connected in series;
• an n-channel device connected at an output of one of said inverters to provide resistance to a high-to-low transition;
• and
• a p-channel device connected at an output of one of said inverters to provide resistance to a low-to high transition.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus;
• an output device coupled to the processor through the processor bus;
• and
• a memory device coupled to the processor bus, the memory device comprising:
• an array of memory cells;
• an address decoder for receiving an address and for identifying at least a specific cell in said array of memory cells corresponding to said address;
• a read/write circuit for reading information out of and writing information into said specific cell;
• a control logic circuit for receiving command signals and generating control signals in response thereto for controlling said address decoder and said read/write circuit;
• and
• a clock circuit for producing clocking signals for input to said control logic, said clock circuit including a path for delaying the clock signal comprising:
• at least three inverters connected in series;
• and
• at least one transistor connected to oppose a transition of the output of one of said inverters.