Semiconductor memory device

A semiconductor memory comprising:

• a plurality of word lines;
• a pair of complementary bit lines;
• a plurality of dynamic memory cells connected to said plurality of word lines, respectively;
• a sense amplifier which amplifies a pair of signals appearing on said pair of complementary bit lines;
• and
• a pair of MOSFETs interposed between a pair of sense nodes of said sense amplifier and said pair of complementary bit lines, which MOSFETs receive a control signal at their gates,
• wherein said control signal is selectively set to one of a select level, an unselect level and an intermediate level between said select level and said unselect level,
• wherein, after said pair of signals have appeared on said pair of complementary bit lines by selecting one of said plurality of word lines, said control signal is changed from said select level to said intermediate level, and
• wherein, after the start of the operation of said sense amplifier, said control signal is returned from said intermediate level to said select level.

A semiconductor memory comprising:

• a pair of complementary bit lines;
• a plurality of word lines crossing said pair of complementary bit lines;
• a plurality of dynamic memory cells each of which is connected to a corresponding one of said plurality of word lines and a corresponding one of said pair of data lines;
• a sense amplifier which amplifies a pair of signals appearing on said pair of complementary bit lines;
• and
• a pair of MOSFETs interposed between a pair of sense nodes of said sense amplifier and said pair of complementary bit lines, which MOSFETs receive a control signal at their gates,
• wherein said control signal is selectively set to one of a select level, an unselect level and an intermediate level between said select level and said unselect level,
• wherein, after said pair of signals have appeared on said pair of complementary bit lines by selecting one of said plurality of word lines, said control signal is changed from said select level to said intermediate level,
• wherein, after the start of the operation of said sense amplifier, said control signal is returned from said intermediate level to said select level, and
• wherein said control signal is set to said unselect level when each of said plurality of word lines is supposed to be unselected.

A semiconductor memory comprising:

• a pair of complementary bit lines;
• a plurality of word lines crossing said pair of complementary bit lines;
• a plurality of dynamic memory cells each of which is connected to a corresponding one of said plurality of word lines and a corresponding one of said pair of data lines;
• a sense amplifier which amplifies a pair of signals appearing on said pair of complementary bit lines;
• and
• a pair of N-channel MOSFETs interposed between a pair of sense nodes of said sense amplifier and said pair of complementary bit lines, which MOSFETs receive a control signal at their gates,
• wherein said control signal is selectively set to one of a high level, a low level and an intermediate level between said high level and said low level,
• wherein, after said pair of signals have appeared on said pair of complementary bit lines by selecting one of said plurality of word lines, said control signal is changed from said high level to said intermediate level,
• wherein, after the start of the operation of said sense amplifier, said control signal is returned from said intermediate level to said high level, and
• wherein said control signal is set to said low level when each of said plurality of word lines is supposed to be unselected.