Semiconductor memory device and storage method thereof

A semiconductor memory device comprising:

• memory cells having n states including state “0”, state “1”, . . . and state “n−1” (2≦n, n being a natural number);
• a first data storage circuit for storing externally input data, said data being of the first logic level or of the second logic level;
• read circuits for reading the state of said memory cells;
• a second data storage circuit for storing data of the first logic level when the state of said memory cells read out by said read circuits is at any of “0” through “i” but storing data of the second logic level when the state of said memory cells read out by said read circuits is at any of “i” through “n−1”;
• write circuits for modifying the state of the memory cells from state “i−1” to state “1” when the data of said first data storage circuit are of the first logic level but holding the state of the memory cells when the data of said first data storage circuit are of the second logic level;
• a write verify circuit for shifting the data of said first data storage circuit from the first logic level to the second logic level when the state of said memory cells has already got to state “i” and the data of said second data storage circuit are of the first logic level but holding the data of said first data storage circuit when the state of said memory cells has not got to state “i” yet and the data of said second data storage circuit are of the first logic level and also when the data of said second data storage circuit are of the second level;
• and
• a write state control circuit for controlling the sate of said memory cells so as not to be modified from “i+1” to “n−1” even temporarily when the state of said memory cells is modified from “i−1” to “i”.

A semiconductor memory device comprising:

• memory cells having n states including state “0”, state “1”, . . . and state “n−1” (2≦n, n being a natural number);
• a differential amplifier circuit having at least a differential amplifier for being fed with the potential output from said memory cells at the first input terminal thereof and a reference potential different from said potential at the second input terminal thereof;
• a logic circuit for selectively taking out the output signal of said at least one differential amplifier;
• a data storage circuit connected to said memory cells for storing data of the first logic level or of the second logic level;
• and
• control circuits for modifying the state of said memory cells from “i−1” to “i” when the data of said data storage circuit are of the first logic level, maintaining the state of said memory cells when the data of said data storage circuit are of the second logic level, shifting the data of said data storage circuit from the first logic level to the second logic level when the state of said memory cells have already got to state “i” and currently is at any of “1” through “i”, holding the data of said data storage circuit to the first logic level when the state of said memory cells have not got to state “i” yet and currently is at any of “1” through “i”, holding the data of said data storage circuit when the state of said memory cells are at any of “i+1” through “n−1” and controlling the sate of said memory cells so as not to be modified from “i+1” to “n−1” even temporarily when the state of said memory cells is modified from “i−1” to “i”.

A storage method of a memory device comprising memory cells adapted to have n-valued states, said method comprising:

• storing externally input data of the first logic level or of the second logic level in the data storage circuits of the device;
• shifting the logic level stored in said data storage circuits in response to the first logic level or the second logic level read out from said memory cells;
• and
• modifying the state of said memory cells when said shifted logic level stored in said data storage circuits is the first logic level but holding the state of said memory cells when said shifted logic level stored in said data storage circuits is the second logic level.