Nmos precharge domino logic

An integrated circuit, comprising:

• a first input connection for receiving a clock signal;
• a second input connection for receiving an input data signal;
• and
• a domino logic circuit coupled to receive the input clock signal and the data signal, the domino logic circuit including a dynamic stage having an n-channel transistor coupled between a first voltage supply and a dynamic output node and a gate of the transistor coupled to the dynamic output node.

A method of operating a domino logic circuit, comprising:

• receiving an inverse clock signal via a first n-channel transistor coupled between a first voltage supply and a dynamic output node;
• charging the dynamic output node of the domino logic circuit via the first n-channel transistor when the inverse clock signal is high;
• receiving an input data signal via a pull-down circuit connected between the dynamic output node and a second voltage supply;
• and
• evaluating the input data signal by selectively coupling the dynamic output node to the second voltage source in response to the input data signal when the inverse clock signal is low.

A circuit, comprising:

• an n-channel clock transistor coupled between a dynamic output node and a first supply voltage, a gate of the n-channel clock transistor coupled to receive an inverse clock signal;
• a first inverter and a second inverter connected in series, an input of the first inverter connected to an output of the second inverter, and an input of the second inverter connected to the dynamic output node;
• an n-channel level keeper transistor coupled between the dynamic output node and the first supply voltage, the gate of the n-channel level keeper transistor coupled to the output of the first inverter;
• a pull-down circuit connected between the dynamic output node and a second supply voltage;
• a static CMOS circuit, an input of which is connected to the dynamic output and an output of which provides an output signal;
• and
• a p-channel transistor coupled between the first voltage supply and the dynamic output node, a gate of the p-channel standby transistor coupled to receive an inverse standby signal.

A circuit, comprising:

• an n-channel clock transistor coupled between a dynamic output node and a first supply voltage, a gate of the n-channel clock transistor coupled to receive an inverse clock signal;
• a first inverter and a second inverter connected in series, an input of the first inverter connected to an output of the second inverter, and an input of the second inverter connected to the dynamic output node, and the output of the second inverter providing a logic circuit output signal;
• an n-channel level keeper transistor coupled between the dynamic output node and the first supply voltage, the gate of the n-channel level keeper transistor coupled to the output of the first inverter;
• a pull-down circuit connected between the dynamic output node and a second supply voltage;
• and
• a p-channel transistor coupled between the first voltage supply and the dynamic output node, a gate of the p-channel standby transistor coupled to receive an inverse standby signal.