Interconnection and input/output resources for programable logic integrated circuit devices

A programmable logic integrated circuit device comprising:

• a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions;
• a plurality of signal conductors extending perpendicular to said rows adjacent to the midpoint of said rows;
• a plurality of branch conductors branching from said signal conductors adjacent to each of said rows and extending along the adjacent row, the branching conductors adjacent to each row being configured to convey signals from the signal conductors to the regions in the adjacent row;
• and
• a plurality of input pins disposed adjacent to the center of the device and configured to respectively supply signals received from circuitry external to the device to said signal conductors.

A programmable logic integrated circuit device comprising:

• a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of said regions;
• a plurality of input pins disposed adjacent to the center of the device and configured to receive signals from circuitry external to the device;
• first programmable logic connector circuitry configured to select fast conductor signals from the signals received by the input pins and signals output by a subplurality of said regions that are adjacent to the center of the device;
• a plurality of fast conductors extending perpendicular to said rows adjacent to the midpoint of the rows and configured to convey the fast conductor signals selected by the first programmable logic connector circuitry;
• a plurality of branch conductors adjacent to each of said rows and extending along the adjacent row, the branch conductors adjacent to each row being configured to convey signals to the regions in the adjacent row;
• and
• second programmable logic connector circuitry associated with each of said rows and configured to selectively apply fast conductor signals from the fast conductors to the branch conductors adjacent the row that the second programmable logic connector circuitry is associated with.

A programmable logic integrated circuit device comprising:

• a plurality of logic regions disposed on the device in a two-dimensional array of rows and columns of the logic regions;
• a plurality of cells of input/output circuitry disposed between two of the rows of the logic regions;
• a plurality of conductors that extend horizontally and vertically adjacent to the logic regions and the cells;
• and
• a plurality of programmable logic connectors that are configured to selectively apply signals to the conductors and configured to receive the signals from at least the logic regions.