Memories having reduced bitline voltage offsets
AssigneeArtisan Components, Inc.
InventorScott T. Becker
Life of this patent
Estimating the term…
Abstract
A memory device design is provided. The memory device includes a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The memory device further includes a core cell having a bitline and a complementary bitline, and a flipped core cell that has a flipped bitline and a flipped complementary bitline. The multiple pairs of the global bitline and the global complementary bitline have a plurality of core cells that are defined by alternating ones of the core cell and the flipped core.
Claims11
A memory device having equalized bitline capacitance;
- comprising:
- a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline;
- a core cell having a bitline and a complementary bitline;
- a flipped core cell that has a flipped bitline and a flipped complementary bitline, the multiple pairs of the global bitline and the global complementary bitline have a plurality of core cells that are defined by alternating ones of the core cell and the flipped core.
A memory device;
- comprising:
- a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline;
- a core cell having a bitline and a complementary bitline;
- a flipped core cell that has a flipped bitline and a flipped complementary bitline;
- and
- a plurality of the core cell in a column and a plurality of the flipped core cell are arranged in the column, such that the plurality of the core cell equals the plurality of the flipped core cell.
Dependencies are inferred from the claim text.