Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same

A memory device, comprising:

• a control circuit adapted to receive a command from an external source and generate control signals responsive thereto, the control circuit including a clock generator circuit adapted to receive at least one external clock signal and to generate an internal clock signal, a read clock signal, and a write clock signal in which the internal clock signal, read clock signal, and write clock signal may be in different clock domains, the control circuit further generating a read data start signal to initiate transfer of data from the memory device and a write data start signal to initiate transfer of data to the memory device;
• a memory array coupled to the control circuit, the memory array having a plurality of memory cells adapted to store write data responsive to a first input data clock signal derived from the internal clock signal and to output read data responsive to a first output data clock signal derived from the internal clock signal;
• an addressing circuit coupled to the memory array and the control circuit, the addressing circuit adapted to receive addresses from an external source and select a memory cell in the memory array corresponding thereto;
• a read data path having a read register coupled to the control circuit, the read register being adapted to receive read data from the memory array responsive to a second input data clock signal derived from the read clock signal, and to couple the read data to an externally accessible terminal responsive to a second output data clock signal derived from the read clock signal, at least one of the data clock signals being generated subsequent to the read data start signal;
• a write data path having a write register coupled to the control circuit, the write register being adapted to receive write data from an externally accessible terminal responsive to a third input data clock signal derived from the write clock signal, and to couple the write data to the memory array responsive to a third output data clock signal derived from the internal clock signal, at least one of the data clock signals being generated subsequent to the write data start signal;
• and
• a coupling system for generating at least one of the data clock signals, the coupling system comprising:
• a phase comparator receiving signals indicative of the relative phase of the internal clock signal and one of the read and write clock signals, the phase comparator generating a phase signal indicative of whether or not the internal clock signal leads the one of the read and write clock signals;
• a state machine receiving one of the start signals, the internal clock signal, and one of the read or write clock signals, the state machine generating one of the data clock signals from one of the internal, read, or write clock signals, the data clock signal being generated at a time subsequent to the start signal as a function of whether or not the internal clock signal leads the read or write clock signal received by the state machine.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• a memory controller coupled to the processor through the processor bus;
• and
• a memory device coupled to the processor through the processor bus, comprising:
• a control circuit adapted to receive a command from an external source and generate control signals responsive thereto, the control circuit including a clock generator circuit adapted to receive at least one external clock signal and to generate an internal clock signal, a read clock signal, and a write clock signal in which the internal clock signal, read clock signal, and write clock signal may be in different clock domains, the control circuit further generating a read data start signal to initiate transfer of data from the memory device and a write data start signal to initiate transfer of data to the memory device;
• a memory array coupled to the control circuit, the memory array having a plurality of memory cells adapted to store write data responsive to a first input data clock signal derived from the internal clock signal and to output read data responsive to a first output data clock signal derived from the internal clock signal;
• an addressing circuit coupled to the memory array and the control circuit, the addressing circuit adapted to receive addresses from an external source and select a memory cell in the memory array corresponding thereto;
• a read data path having a read register coupled to the control circuit, the read register being adapted to receive read data from the memory array responsive to a second input data clock signal derived from the read clock signal, and to couple the read data to an externally accessible terminal responsive to a second output data clock signal derived from the read clock signal, at least one of the data clock signals being generated subsequent to the read data start signal;
• a write data path having a write register coupled to the control circuit, the write register being adapted to receive write data from an externally accessible terminal responsive to a third input data clock signal derived from the write clock signal, and to couple the write data to the memory array responsive to a third output data clock signal derived from the internal clock signal, at least one of the data clock signals being generated subsequent to the write data start signal;
• and
• a coupling system for generating at least one of the data clock signals, the coupling system comprising:
• a phase comparator receiving signals indicative of the relative phase of the internal clock signal and one of the read and write clock signals, the phase comparator generating a phase signal indicative of whether or not the internal clock signal leads the one of the read and write clock signals;
• a state machine receiving one of the start signals, the internal clock signal, and one of the read or write clock signals, the state machine generating one of the data clock signals from one of the internal, read, or write clock signals, the data clock signal being generated at a time subsequent to the start signal as a function of whether or not the internal clock signal leads the read or write clock signal received by the state machine.

A method of coupling a signal through a circuit responsive to a start signal, comprising:

• generating the start signal;
• clocking the signal into the circuit using a first clock signal operating in a first clock domain, the signal being clocked into the circuit a first number of transitions of the first clock signal after start signal;
• clocking the signal out of the circuit using a second clock signal operating in a second clock domain, the signal being clocked out of the circuit a second number of transitions of the second clock signal after start signal;
• determining whether the first clock signal leads the second clock signal;
• and
• altering either the first number of transitions or the second number of transitions depending on whether or not the first clock signal leads the second clock signal.

A method of coupling data from a first circuit operating in one clock domain defined by a first clock signal to a second circuit operating in a second clock domain defined by a second clock signal, the method comprising:

• clocking the data out of the first circuit responsive to a clock signal synchronized to the first clock signal;
• clocking the data into of the second circuit responsive to a clock signal synchronized to the second clock signal;
• determining whether the first clock signal leads the second clock signal;
• and
• adjusting a delay period between clocking the data out of the first circuit and clocking the data into the second circuit, the delay period when the first clock signal leads the second clock signal being shorter than when the first clock signal does not lead the second clock signal.

In a packetized dynamic random access memory (“DRAM”) having a plurality of memory arrays from which read data is output responsive to an internal clock signal operating in one clock domain, the packetized DRAM further including a read buffer coupled to the memory arrays to which read data is transferred responsive to a data clock signal operating in a different clock domain, a method of transferring the read data from the memory arrays to the read buffer, comprising:

• clocking the read data out of the memory arrays responsive to the internal clock signal;
• clocking the read data into of the read buffer responsive to the data clock signal;
• determining whether the internal clock signal leads the data clock signal;
• and
• adjusting a delay period between clocking the read data out of the memory arrays and clocking the read data into the read buffer, the delay period when the internal clock signal leads the data clock signal being shorter than when the internal clock signal does not lead the data clock signal.

In a packetized dynamic random access memory (“DRAM”) having a read buffer into which read data is clocked responsive to a data clock signal operating in one clock domain and out of which read data is clocked responsive to a read clock signal operating in a different clock domain, a method of transferring the read data through the read buffer, comprising:

• clocking the read data into the read buffer responsive to the data clock signal;
• clocking the read out of the read buffer responsive to the read clock signal;
• determining whether the data clock signal leads the read clock signal;
• and
• adjusting a delay period between clocking the read data into the read buffer and clocking the read data out of the read buffer, the delay period when the data clock signal leads the read clock signal being shorter than when the data clock signal does not lead the read clock signal.

In a packetized dynamic random access memory (“DRAM”) having a write buffer into which write data is clocked responsive to a first clock signal operating in one clock domain and out of which write data is clocked responsive to a write clock signal operating in a different clock domain, a method of transferring the write data through the write buffer, comprising:

• clocking the write data into the write buffer responsive to the first clock signal;
• clocking the write out of the write buffer responsive to the write clock signal;
• determining whether the first clock signal leads the write clock signal;
• and
• adjusting a delay period between clocking the write data into the write buffer and clocking the write data out of the write buffer, the delay period when the first clock signal leads the write clock signal being shorter than when the first clock signal does not lead the write clock signal.