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US 2002/0055233 A1Published application
Higher voltage drain extended MOS transistors with self-aligned channel and drain extensions
AssigneeTexas Instruments Incorporated
InventorJozef Czeslaw Mitros
Life of this patent
Estimating the term…
Abstract
An integrated circuit drain extension transistor. A transistor gate (72) is formed over a CMOS n-well region (10). A transistor source extension region (50), and drain extension region (52) are formed in the CMOS well region (10). A transistor region (90) is formed in the source extension region 50 and a transistor drain region 92 is formed between two drain alignment structures (74), (76) in the drain extension region (52).
Claims23
A method for forming a drain extension transistor, comprising:
- providing a semiconductor substrate with a plurality of isolation structures and a first well region of a first conductivity type;
- forming a masking layer on a first area of said first well region;
- implanting said first well region to form regions of a second conductivity type in said first well region adjacent to said masking layer;
- removing said masking region;
- forming a gate dielectric on said first well region;
- forming a gate layer on said gate dielectric;
- patterning said gate layer to form a gate structure and drain alignment structures such that said gate structure overlies a portion of said first well region and a portion of said regions of said second conductivity type;
- forming a patterned film to mask an area between said gate structure and said drain alignment structures;
- and
- simultaneously forming a source region and a drain region in said regions of said second conductivity type.
7 more elements
A method for forming a drain extension transistor, comprising:
- providing a semiconductor substrate with a plurality of isolation structures and a first well region of a first conductivity type;
- forming a masking layer on a first area of said first well region;
- implanting said first well region to form regions of a second conductivity type in said first well region adjacent to said masking layer;
- removing said masking region;
- forming a gate dielectric on said first well region;
- forming a gate layer on said gate dielectric;
- patterning said gate layer to form a gate structure such that said gate structure overlies a portion of said first well region and a portion of said regions of said second conductivity type and a portion of at least one of said isolation structures;
- and
- simultaneously forming a source region and a drain region in said regions of said second conductivity type.
6 more elements
A transistor, comprising:
- a silicon substrate comprising a plurality of isolation structures and a well region of a first conductivity type;
- a gate dielectric layer over said well region;
- a first and second doped region of a second conductivity type contained in said well region, and separated by a first distance;
- a gate layer and at least a first and second drain alignment structure wherein said gate layer is over a portion of said well region and overlaps a portion of said first doped region and portion of said second doped region, and said first and second drain alignment structures are over said second doped region;
- a source region of a second conductivity type contained within said first doped region;
- and
- a drain region of a second conductivity type contained within said second doped region and positioned between said first and second drain alignment structures.
4 more elements
A transistor, comprising:
- a silicon substrate comprising a plurality of isolation structures and a well region of a first conductivity type;
- a gate dielectric layer over said well region;
- a first and second doped region of a second conductivity type contained in said well region, and separated by a first distance wherein said second doped region contains at least one of said plurality of said isolation structures;
- a gate layer wherein said gate layer is over a portion of said well region and overlaps a portion of said first doped and a portion of said isolation structure contained in said second doped region;
- a source region of a second conductivity type contained within said first doped region;
- and
- a drain region of a second conductivity type contained within said second doped region and positioned between said isolation structure contained in said second doped region and a second of said plurality of isolation structures;
4 more elements
A transistor, comprising:
- a substrate containing a well region of a first conductivity type;
- a gate layer and drain alignment structures over said well region;
- and
- a source region adjacent to said gate layer and a drain region positioned between said drain alignment structures wherein said source and drain regions are separated by a first distance.
1 more element
Dependencies are inferred from the claim text.