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US 2002/0055231 A1Published application
Semiconductor structure having more usable substrate area and method for forming same
AssigneeMicron Technology, Inc.
InventorDarwin A. Clampitt
Life of this patent
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Abstract
A semiconductor structure includes a first substrate portion having a surface and a first active region disposed in the first substrate portion. An insulator region is disposed on the first substrate portion outside of the first active region and extends out from the surface. A second substrate portion is disposed on the insulator region, and a second active region is disposed in the second substrate portion. Thus, by disposing a portion of the substrate on the isolation region, the usable substrate area is dramatically increased.
Claims42
A semiconductor structure, comprising:
- a first portion of a substrate having a surface;
- a first active region disposed in the first portion of the substrate;
- an isolation region disposed on the first portion of the substrate outside of the first active region and extending out from the surface;
- a second portion of the substrate disposed on the isolation region;
- and
- a second active region disposed in the second portion of the substrate.
3 more elements
A semiconductor structure, comprising:
- a first portion of a substrate having a surface occupying a first area;
- first active regions disposed in the first substrate portion and occupying a second area;
- isolation regions disposed on the first substrate portion outside of the first active regions and extending out from the surface of the first substrate portion, the isolation regions occupying a third area;
- a second portion of the substrate disposed on the isolation regions;
- and
- second active regions disposed in the second substrate portion and occupying a fourth area, the sum of the second and fourth areas being significantly greater than the difference between the first and third areas.
3 more elements
A semiconductor structure, comprising:
- a first portion of a substrate, the first portion having a surface of a first area;
- dielectric runners extending out from the surface and being substantially parallel to one another, the dielectric runners defining trenches therebetween, the trenches having bottoms formed by the surface, the dielectric runners occupying a second area and the trench bottoms occupying a third area;
- recessed active regions formed in the trench bottoms and occupying a fourth area;
- a second portion of the substrate disposed on the dielectric runners;
- and
- elevated active regions disposed in the second substrate portion and occupying a fifth area.
3 more elements
A memory array, comprising:
- a first portion of a substrate having a surface;
- dielectric runners extending out from the surface and being substantially parallel to one another, the dielectric runners defining trenches therebetween, the trenches having bottoms formed by the surface;
- recessed memory cells disposed in the trench bottoms;
- a second portion of the substrate disposed on the dielectric runners;
- elevated memory cells disposed in the second substrate portion;
- and
- word lines each extending substantially orthogonal to the dielectric runners and disposed over recessed and elevated memory cells to define a respective row of memory cells.
4 more elements
A memory circuit, comprising:
- a semiconductor substrate;
- address, data, and command busses disposed on the substrate;
- an address decoder disposed in the substrate and coupled to the address bus;
- a read/write circuit disposed in the substrate and coupled to the address decoder;
- a data input/output circuit disposed in the substrate and coupled to the data bus and to the read/write circuit;
- a control circuit disposed in the substrate and coupled to the command bus, to the address decoder, to the read/write circuit, and to the data input/output circuit;
- and
- an array of memory cells arranged in rows and columns and coupled to the address decoder and the read/write circuit, the array including,
- a first portion of the substrate having a surface;
- dielectric runners extending out from the surface and being substantially parallel to one another, the dielectric runners defining trenches therebetween, the trenches having bottoms formed by the surface;
- recessed memory cells disposed in the trench bottoms;
- a second portion of the substrate disposed on the dielectric runners;
- elevated memory cells disposed in the second substrate portion;
- and
- word lines each extending substantially orthogonal to the dielectric runners and disposed over recessed and elevated memory cells to define a respective one of the rows.
12 more elements
An electronic system, comprising:
- a data input device;
- a data output device;
- and
- computing circuitry coupled to the data input and output devices, the computing circuitry including a memory circuit that includes:
- a semiconductor substrate;
- address, data, and command busses disposed on the substrate;
- an address decoder disposed in the substrate and coupled to the address bus;
- a read/write circuit disposed in the substrate and coupled to the address decoder;
- a data input/output circuit disposed in the substrate and coupled to the data bus and to the read/write circuit;
- a control circuit disposed in the substrate and coupled to the command bus, to the address decoder, to the read/write circuit, and to the data input/output circuit;
- an array of memory cells arranged in rows and columns and coupled to the address decoder and the read/write circuit, the array including,
- a first portion of the substrate having a surface;
- dielectric runners extending out from the surface and being substantially parallel to one another, the dielectric runners defining trenches therebetween, the trenches having bottoms formed by the surface;
- recessed memory cells disposed in the trench bottoms;
- a second portion of the substrate disposed on the dielectric runners;
- elevated memory cells disposed in the second substrate portion;
- and
- word lines each extending substantially orthogonal to the dielectric runners and disposed over recessed and elevated memory cells to define a respective one of the rows.
15 more elements
A method for forming a semiconductor structure, comprising:
- forming tapered towers in a semiconductor substrate;
- forming an insulator layer on the substrate;
- anisotropically etching the insulator layer;
- and
- forming active regions in the substrate on top of and between the towers.
2 more elements
A method for forming a semiconductor structure, comprising:
- forming alternating and substantially parallel runners and trenches in a semiconductor substrate, the runners having side walls that taper toward the substrate, the runners having tops and the trenches having bottoms that face away from the substrate;
- forming a dielectric layer on the runners and in the trenches;
- removing the dielectric layer from the tops of the runners and the bottoms of the trenches and leaving the dielectric layer on the side walls;
- and
- forming active regions in the tops of the runners and bottoms of the trenches.
2 more elements
A method for forming a memory array, comprising:
- forming alternating and substantially parallel runners and trenches in a semiconductor substrate, the runners having side walls that taper toward the substrate, the runners having tops and the trenches having bottoms that face away from the substrate;
- forming a dielectric layer on the runners and in the trenches;
- removing the dielectric layer from the tops of the runners and the bottoms of the trenches and leaving the dielectric layer on the side walls;
- forming a gate dielectric on the tops of the runners and on the bottoms of the trenches;
- forming on the gate dielectric word lines that are substantially perpendicular to the runners and trenches;
- and
- forming memory-cell-transistor source/drain regions adjacent to the word lines in the tops of the runners and in the bottoms of the trenches.
4 more elements
Dependencies are inferred from the claim text.