US 2002/0055217 A1 · Semiconductor device and its manufacturing method

Abstract

A semiconductor device including memory cells isolated by a trench that may be self aligned with a stacked film pattern (7) has been disclosed. The memory cells may be flash memory cells having an active gate film (2) that may be thinner than a gate oxide film (30). The active gate film (2) may be located in a central portion under of a gate electrode (3). The gate oxide film (30) may be located under end portions of the gate electrode (3). In this way, a distance between a shoulder portion of a trench (11) and a gate electrode (3) may be increased. Thus, an electric field concentration in the shoulder portion of the trench (11) may be decreased and memory cell characteristics may be improved.

Claims20

Dependent claims

A semiconductor device, comprising:

a semiconductor substrate;
an isolation film buried in the substrate;
a gate insulating film formed between the isolation film and having end portions adjacent to the isolation film that are thicker than a central portion.

Dependencies are inferred from the claim text.

Facts

Application

10/032,764Filed 22 Oct 2001

Priority

JP 2000-32565625 Oct 2000

Published

9 May 2002

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10W 10/012
Of isolation regions comprising dielectric materials: using local oxidation of silicon [LOCOS]
H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations

Semiconductor device and its manufacturing method

Life of this patent

Semiconductor device and its manufacturing method

Life of this patent

Abstract

Claims20