US 2002/0054684 A1 · Process for digital communication and system communicating digitally

Abstract

According to the present invention, a three-line bus is used for communication between a first digital unit (1) and two other digital units (3). The three-line bus includes a system clock line (SCL) as well as a data transmission line (SD) through which data is sent from the two other units (3), i.e. transmitting units, to the first unit (1), i.e. receiving unit. The system uses an authorization line (WS) for determining which of the two transmitting units (3) is capable of writing data on the data transmission line (SD) and when it can do so. The communication form the first unit (1), now operating as a transmitter, to the two other units (3), now operating as receivers, is made possible by the fact that data signals are also injected in the authorization line (WS) and transmitted through said line together with the authorization control signals.

Claims32

Dependent claims

A process for digital communication between

a first unit (DSP 1), which has at least one input (ESD) for serial digital data,
at least two second units (3a,3b) with a data output (ASD) for serial, digital data,
whereby the input (ESD) of the first unit (DSP1) is connected via a common data line (SD) to the outputs (ASD) of the second units (3a, 3b) connected to it, and in the process, serial, digital data are supplied from the second units (3a, 3b) to the first (DSP1) over the data line (SD) mentioned, controlled by a binary permission signal fed to the second units (3a, 3b), connected together over a permission line (WS), and a clock signal fed together to the units connected via a clock line (SCL), characterized by the fact that the first unit (DSP1) communicates with the second (3a, 3b) over the permission line (WS), by superimposing data signals (DA) on the binary permission signal on the first unit (DSP1) and by receiving and evaluating them on the second unit (3a, 3b).

A digitally communicating system, including:

a first digital processing unit (DSP1), which has at least one input (ESD) for serial digital data,
at least two second units that can be connected to one data output (ASD) for serial digital data
whereby the input (ESD) of the first unit (DSP1, DSP1′) is connected over a common data line (SD) to the outputs (ASD) of the second units (3a, 3b) connected, and the first unit (DSP1, DSP1′) is connected by means of a common permission line (WS) to the second units (3a, 3b) connected, whereby the first unit produces a binary permission signal (SWS) on this permission line, and the second units connected controlled by the permission signal, time-staggered for writing data on the common data line (SD) are controlled and released, whereby the units are connected by means of a common clock line (SCL), characterized by the fact that a coding unit (ENC) is provided on the first unit (DSP1) to superimpose data signals on the permission signal (SWS) on the permission line (WS) and by the fact that a decoding unit (DEC) is connected to the input of the permission line (WS) on each second unit connected (3a,3b, 3x), in order to decode data signals (DA) superimposed on the permission signal (SWS) in addition to data write permission (SW).

Dependencies are inferred from the claim text.

Process for digital communication and system communicating digitally

Life of this patent

Process for digital communication and system communicating digitally

Life of this patent

Abstract

Claims32