PLL circuit and optical communication reception apparatus
AssigneeSony Corporation
InventorsToru Takeshita, Takashi Nishimura
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AssigneeSony Corporation
InventorsToru Takeshita, Takashi Nishimura
Estimating the term…
The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, the convergence time required for frequency detection of a frequency detection circuit is short and wrong operation of the frequency detection circuit with a control signal is less likely to occur. A clock generator produces, based on an oscillation frequency clock of a VCO, a first clock signal of the same phase, a second clock signal having a phase delayed by 90 degrees from that of the first clock signal, and a third clock signal having a phase delayed by 45 degrees from that of the first clock signal. A phase detection circuit performs phase control based on the phase difference between the third clock signal and an input signal, and a frequency detection circuit fetches the first and second clock signals in synchronism with the input signal and performs frequency control based on the fetched signals.
A PLL circuit, comprising:
An optical communication reception apparatus, comprising:
Dependencies are inferred from the claim text.