Selective modification of clock pulses
AssigneeSTMicroelectronics S.r.l.
InventorAlan Lloyd
Life of this patent
Estimating the term…
Abstract
A circuit for modifying a clock pulse train is described. The circuit has an input for receiving the clock pulse train, a first logic circuit having an output which is responsive to a clock pulse edge of a first polarity and a second logic circuit having an output which is responsive to a clock pulse edge of a second polarity. A two input multiplexer is provided to receive respectively the outputs of the first and second logic circuits and is arranged to provide an output representing a modification of the input clock pulse train.
Claims13
A circuit for modifying a clock pulse train, the circuit comprising:
- an input for said clock pulse train;
- a first logic circuit having an output which is responsive to a first clock pulse edge of the clock pulse train, the first clock pulse edge having a first polarity;
- a second logic circuit having an output which is responsive to a second clock pulse edge of the clock pulse train, the second clock pulse edge having a second polarity opposite to said first polarity;
- and
- a two-input multiplexer having an output as an output of said circuit, a control input coupled to receive said clock pulse train, a first input receiving the output of the first logic circuit, and a second input receiving the output of the second logic circuit.
A circuit for selectively modifying a clock pulse train, the circuit comprising:
- an input for said clock pulse train;
- a clocked first latch having an input, an output and a clock terminal;
- a clocked second latch having an input, an output and a clock terminal;
- and
- a two input multiplexer having a control input connected to receive said clock pulse train, a first input connected to the output of the first latch, and a second input connected to the output of the second latch, said input for said clock pulse train being connected to the clock terminals of said first and second latches wherein the first latch is responsive to a rising edge in said clock pulse train and the second latch is responsive to a falling edge in said clock pulse train.
A method of selectively modifying a clock pulse train, the method comprising:
- receiving the clock pulse train at respective inputs of first and second logic circuits having respective outputs;
- selectively enabling the first logic circuit with a first enable signal, thereby causing the first logic circuit, when enabled, to output a first portion of the clock pulse train;
- selectively enabling the second logic circuit with a second enable signal, thereby causing the second logic circuit, when enabled, to invert a second portion of the clock pulse train and output the inverted second portion;
- and
- alternately electrically connecting to an output terminal either the output of the first logic circuit or the output of the second logic circuit depending on a logic level of the clock pulse train.
Dependencies are inferred from the claim text.