US 2002/0053696 A1Published application

Semiconductor device having low on resistance high speed turn off and short switching turn off storage time

AssigneeFuji Electric Co., Ltd.

InventorsNORIYUKI IWAMURO, YUICHI HARADA

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Abstract

A semiconductor device is provided which includes a first p base region and a second p base region formed in one of opposite surface of a high-resistance n base region, a p collector region formed on the other surface of the n base region, an n emitter region formed in a surface layer of the first p base region, and a groove formed in the n base region between the first and second p base regions, to provide a trench gate electrode portion. The first and second p base regions are formed alternately in the Z-axis direction with certain spacing therebetween. The second p base region is held in a floating state in terms of the potential, thus assuring a reduced ON-resistance, and a large quantity of carriers present in the vicinity of the surface of the second p base region are quickly drawn away through a p channel upon turn-off, so that the turn-off time is reduced.

Claims10

Dependent claims

A semiconductor device, comprising:

a first-conductivity-type first base region;
a gate electrode formed on a gate insulating film within a groove that is formed in a selected elongate portion of a surface layer of the first base region;
a second-conductivity-type second base region formed in a selected portion of the surface layer of the first base region, such that the second base region has a smaller depth than the groove, and is located adjacent to the groove;
a source region formed in a selected portion of a surface layer of the second base region, to be located adjacent to the groove;
a second-conductivity-type third base region that is formed in a selected portion of the surface layer of the first base region, apart from the second base region, to be located adjacent to the groove;
a first main electrode formed in contact with the source region and the second base region;
a collector region formed in a rear surface layer of the first base region;
and
a second main electrode formed on the collector region;
wherein the second base region and the third base region are alternately formed on at least one of side faces of the groove in a longitudinal direction of the groove.

7 more elements

A method of driving a semiconductor device comprising a first-conductivity-type first base region, a gate electrode formed on a gate insulating film within a groove that is formed in a selected elongate portion of a surface layer of the first base region, a second-conductivity-type second base region formed in a selected portion of the surface layer of the first base region, such that the second base region has a smaller depth than the groove, and is located adjacent to the groove, a source region formed in a selected portion of a surface layer of the second base region, to be located adjacent to the groove, a second-conductivity-type third base region that is formed in a selected portion of the surface layer of the first base region, apart from the second base region, to be located adjacent to the groove, a first main electrode formed in contact with the source region and the second base region, a collector region formed in a rear surface layer of the first base region, and a second main electrode formed on the collector region, wherein the second base region and the third base region are alternately formed on at least one of side faces of the groove in a longitudinal direction of the groove, said method comprising the step of:

driving the semiconductor device so that a channel formed between the second base region and the third base region upon turn-on has a different conductivity type than that formed upon turn-off.

Dependencies are inferred from the claim text.