Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

A memory device, comprising:

• an array of memory cells, each cell including a vertical access transistor formed of a semiconductor pillar that extends outwardly from a substrate with body and first and second source/drain regions, a trench capacitor, and a gate disposed adjacent to a side of the pillar adjacent to the body region wherein a first plate of the trench capacitor is integral with the first source/drain region and a second plate of the capacitor is disposed adjacent to the first plate;
• a number of bit lines that are each selectively coupled to a number of the memory cells at the second source/drain region of the access transistor so as to form columns of memory cells;
• a number of word lines, each word line disposed orthogonally to the bit lines in a trench between rows of the memory cells for addressing gates of the access transistors of the memory cells that are adjacent to the word line;
• and
• a row decoder coupled to the word lines and a column decoder coupled to the bit lines so as to selectively access the cells of the array.

A memory array comprising:

• an array of memory cells, each memory cell including an access transistor having body and first and second source/drain regions vertically formed outwardly from a substrate in a single crystalline semiconductor pillar and a gate disposed adjacent to a side of the transistor, the second source/drain region including an upper semiconductor surface;
• a number of word lines interconnecting gates of selected access transistors so as to form a number of rows of memory cells;
• a number of first isolation trenches separating adjacent rows of memory cells, each isolation trench housing a word line;
• and
• a number of second isolation trenches, each substantially orthogonal to the first isolation trenches and interposed between adjacent memory cells so as to form a number of columns of the array.

A method of fabricating a memory array, the method comprising the steps of:

• forming a number of access transistors, each access transistor formed in a pillar of semiconductor material that extends outwardly from a substrate wherein the access transistor includes a first source/drain region, a body region and a second source/drain region formed vertically thereupon;
• forming a trench capacitor for each access transistor, wherein a first plate of the trench capacitor is integral with the first source/drain region of the access transistor;
• forming a number of word lines, each along a side of one of the pillars, that interconnect the gates of a number of access transistors to form a row of the array, each word line disposed in a trench that separates adjacent rows of access transistors;
• and
• forming a number of bit lines that interconnect second source/drain regions of selected access transistors so as to form a number of columns of the array.

A method of fabricating a memory array, the method comprising the steps of:

• forming a first conductivity type first source/drain region layer on a substrate;
• forming a second conductivity type body region layer on the first source/drain region layer;
• forming a first conductivity type second source/drain region layer on the body region layer;
• forming a number of substantially parallel column isolation trenches extending through the second source/drain region layer, the body region layer, and the first source/drain region layer, thereby forming column bars between the column isolation trenches;
• forming a plurality of substantially parallel row isolation trenches, orthogonal to the column isolation trenches, extending to substantially the same depth as the column isolation trenches, thereby forming an array of vertical access transistors for the memory array;
• filling the row and column isolation trenches with a conductive material to a level that does not exceed the lower level of the body region so as to provide a common plate for capacitors of memory cells of the memory array;
• forming conductive word lines in the row isolation trenches that selectively interconnect access transistors on each row;
• and
• forming bit lines that selectively interconnect the second source/drain regions of the access transistors on each column.