Method for forming contact holes for metal inteconnection in semiconductor devices

A method for forming a metal interconnection contact hole for a semiconductor device, comprising the steps of:

• a) forming a MOS field effect transistor on a semiconductor substrate, the MOS field effect transistor comprising a gate structure with an adjacent contact region;
• b) forming a nitride layer on the MOS field effect transistor;
• c) forming an interlayer insulation layer on the nitride layer;
• d) forming a polysilicon layer on the interlayer insulation layer;
• e) forming a photoresist pattern on the polysilicon layer, the photoresist pattern exposing a portion of the polysilicon layer above the contact region;
• f) etching the exposed portion of the polysilicon layer to form a hard mask using the photoresist pattern as an etching mask;
• f) etching the interlayer insulation layer using the photoresist pattern and the polysilicon pattern as etching masks to expose a portion of the nitride layer;
• g) removing the photoresist pattern and the polysilicon pattern;
• and
• h) etching the exposed portion of the nitride layer to form the metal interconnection contact hole and thereby expose a portion of the contact region of the semiconductor substrate, using an etch having a nitride etch rate that is greater than a interlayer insulation etch rate.

A method for forming a substrate contact to a contact region of a semiconductor substrate comprising the following sequence of steps:

• a) forming a thin oxide layer on the contact region;
• b) forming a nitride layer on the thin oxide layer;
• c) forming an interlayer insulation layer on the nitride layer;
• d) forming a polysilicon layer on the interlayer insulation layer;
• e) forming a photoresist layer on the polysilicon layer;
• patterning the photoresist layer to form a photoresist pattern, the photoresist pattern exposing a portion of the polysilicon layer above the contact region;
• f) etching the polysilicon layer using the photoresist pattern as an etch mask to form a polysilicon pattern, the polysilicon pattern exposing a portion of the interlayer insulation layer above the contact region;
• g) etching the interlayer insulation layer to expose a portion of the nitride layer above the contact region using the polysilicon pattern as an etch mask, the etch conditions providing an interlayer insulation layer etch rate and a nitride layer etch rate, the interlayer insulation etch rate being greater than the nitride layer etch rate;
• h) removing the photoresist pattern;
• i) removing the polysilicon pattern, thereby exposing a surface of the interlayer insulator layer;
• j) etching the exposed portion of the nitride layer to expose a portion of the thin oxide layer above the contact region;
• k) etching the exposed portion of the thin oxide layer to complete a contact opening and expose a portion of the contact region;
• and
• l) forming a layer of conductive material on the exposed surface of the interlayer insulating layer, in the contact opening, and on the exposed portion of the contact region.