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US 2002/0001938 A1Published application
Process for fabricating semiconductor integrated circuit device having polycide line and impurity region respectively exposed to contact holes different in depth
AssigneeNEC Corporation
InventorYASUSHI YAMAZAKI
Life of this patent
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Abstract
When contact holes are concurrently formed in an inter-level insulating layer over an impurity region in a silicon substrate and a polycide line on a thick field oxide layer, the manufacturer interrupts the etching at the refractory metal silicide layer of the polycide line, and restarts the etching after removal of a part of the refractory metal silicide layer exposed to the short contact hole, thereby preventing the impurity region from undesirable etching for the refractory metal silicide layer.
Claims25
A process for fabricating a semiconductor device, comprising the steps of:
- a) preparing a semiconductor structure including a first lower-level conductive line having a semiconductor layer and a refractory metal silicide layer laminated on said semiconductor layer and a second lower-level conductive line without a refractory metal silicide layer;
- b) forming an inter-level insulating layer over said semiconductor structure having a first portion over said first lower-level conductive line and a second portion over said second lower-level conductive line;
- c) etching said first portion and said second portion until said refractory metal silicide layer of said first lower-level conductive line is exposed to a first contact hole, said second lower-level conductive line being still covered with a remaining second portion;
- d) removing a part of said refractory metal silicide layer exposed to said first contact hole from said first lower-level conductive line;
- and
- e) etching said remaining second portion for exposing said second lower-level conductive line to a second contact hole.
3 more elements
Dependencies are inferred from the claim text.