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US 2002/0001904 A1Published application
Semiconductor memory device including spare memory cell
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTakehiro Ochi, Hisao Kobashi
Life of this patent
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Abstract
A redundancy row decoder in a DRAM includes a plurality of N channel MOS transistors connected in series between one terminal of each fuse and a line of a ground potential, the plurality of N channel MOS transistors having their gates receiving a predecode signal allocated to a corresponding word line. As compared with a conventional case where only one N channel MOS transistor is connected between one terminal of each fuse and the line of the ground potential, leakage current flowing through each fuse is made smaller.
Claims7
A semiconductor memory device, comprising:
- a plurality of memory cells to each of which a unique address signal is allocated in advance;
- a spare memory cell for replacing a defective memory cell of said plurality of memory cells;
- a decoder provided corresponding to each memory cell, and activating a corresponding memory cell in response to the address signal allocated to the corresponding memory cell being applied;
- a redundancy decoder inactivating said decoder and activating said spare memory cell in response to the address signal allocated to said defective memory cell being applied;
- and
- a write/read circuit writing and reading data of the memory cell activated by said decoder and the memory cell activated by said redundancy decoder,
- said redundancy decoder including
- a precharge circuit activated before said address signal is applied and charging an output node to a first potential,
- a fuse provided corresponding to each memory cell, having one terminal connected to the output node of said precharge circuit, and blown when a corresponding memory cell is defective,
- a plurality of transistors provided corresponding to each memory cell, connected in series between another terminal of a corresponding fuse and a line of a second potential, and rendered conductive in response to the address signal allocated to a corresponding memory cell being applied, and
- a driver activating said spare memory cell when the output node of said precharge circuit has said first potential after said address signal is applied.
8 more elements
A semiconductor memory device, comprising:
- a plurality of memory cells to each of which a unique address signal is allocated in advance;
- a spare memory cell for replacing a defective memory cell of said plurality of memory cells;
- a decoder provided corresponding to each memory cell and activating a corresponding memory cell in response to the address signal allocated to the corresponding memory cell being applied;
- a redundancy decoder inactivating said decoder and activating said spare memory cell in response to the address signal allocated to said defective memory cell being applied;
- and
- a write/read circuit writing and reading data of the memory cell activated by said decoder and the spare memory cell activated by said redundancy decoder,
- said redundancy decoder including
- a precharge circuit activated before said address signal is applied and charging an output node to a first potential,
- a fuse provided corresponding to each memory cell, having one terminal connected to the output node of said precharge circuit, and blown when a corresponding memory cell is defective,
- a first transistor provided corresponding to each memory cell, having a first electrode connected to another terminal of a corresponding fuse, and rendered conductive in response to the address signal allocated to a corresponding memory cell being applied,
- a second transistor connected between a second electrode of said first transistor and a line of a second potential and rendered non-conductive while said precharge circuit is active, and
- a driver activating said spare memory cell when the output node of said precharge circuit has said first potential after said address signal is applied.
9 more elements
Dependencies are inferred from the claim text.