Semiconductor integrated circuit device and a method of manufacturing the same
OwnerFumitoshi Itoinventor
Life of this patent
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Abstract
A semiconductor integrated circuit device comprises a p-channel MISFET and/or an n-channel MISFET, of which an SRAM cell is constituted and which is arranged to have an offset structure, and MISFET for selection of SRAM cells and MISFET constituting a peripheral circuit of SRAM or a logic circuit which is arranged to have a non-offset structure. At least one of MISFET's constituting an SRAM cell is arranged to take a measure against GIDL (gate induced drain leakage) current.
Claims51
A semiconductor integrated circuit device comprising:
- a plurality of complementary field effect transistors based SRAM cells each constituted of a plurality of field effect transistors and formed on a semiconductor substrate, wherein at least one first field effect transistor selected from among the plurality of field effect transistors has a pair of semiconductor regions constituting a source and a drain thereof in such a way that end portions at a channel forming region side of the pair of semiconductor regions are located in a direction kept away from opposite ends of a gate electrode so as not to be superposed with the gate electrode of the first field effect transistor;
- and
- a second field effect transistor, which is formed on said semiconductor substrate and is other than said at least one first field effect transistor, having a pair of semiconductor regions wherein end portions at a channel forming region side of said pair of semiconductor regions are partially superposed with a gate electrode of said at least one first field effect transistor.
A semiconductor integrated circuit device comprising:
- a plurality of complementary field effect transistors based SRAM cells each constituted of a plurality of field effect transistors and formed on a semiconductor substrate, wherein at least one first field effect transistor selected from among the plurality of field effect transistors has a source or drain region in an offset structure with a gate electrode.
A semiconductor integrated circuit device comprising:
- a plurality of complementary field effect transistors based SRAM cells each constituted of a plurality of field effect transistors and formed on a semiconductor substrate, wherein at least one first field effect transistor selected from among the plurality of field effect transistors has a thickness greater than a gate insulating film of a second field effect transistor which is formed on the semiconductor substrate, is other than said at least one first field effect transistor and is supplied with the same source voltage as said at least one first field effect transistor.
A semiconductor integrated circuit device comprising:
- a plurality of complementary field effect transistors based SRAM cells each constituted of a plurality of field effect transistors and formed on a semiconductor substrate, wherein at least one first field effect transistor selected from among the plurality of field effect transistors has a semiconductor region for source or drain having a first semiconductor region of a relatively low impurity concentration located at a channel forming region side and a second semiconductor region of a relatively high impurity concentration connected to said first semiconductor region;
- and
- a second field effect transistor which is formed on said semiconductor substrate, is other than said at least one first field effect transistor and is supplied with the same source voltage as said at least one first field effect transistor, said second field effect transistor including a semiconductor region for source or drain that has a first semiconductor region of a relatively low impurity concentration located at a channel forming region side and a second semiconductor region of a relatively high impurity concentration connected to said first semiconductor region,
- wherein the impurity concentration of said first semiconductor region of said at least one first field effect transistor is lower than the impurity concentration of said first semiconductor region of said second field effect transistor.
A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:
- forming, on a semiconductor substrate, a plurality of field effect transistors constituting each of a plurality of complementary field effect transistors based SRAM cells and a plurality of field effect transistors constituting circuits other than said SRAM cells;
- and
- forming semiconductor regions of at least one first field effect transistor selected from among the plurality of field effect transistors and a second field effect transistor selected from among the plurality of field effect transistors and other than said at least one first field effect transistor in such a way that a semiconductor region for source or drain and a gate electrode of said at least one first field effect transistor are arranged to be offset, and a semiconductor region for source or drain and a gate electrode of said second field effect transistor are arranged to be non-offset.
A method for manufacturing a semiconductor integrated circuit decide, comprising the steps of:
- (a) forming gate insulating films of first and second field effect transistors on a semiconductor substrate;
- (b) forming gate electrodes of said first and second field effect transistors on the gate insulating films, respectively;
- (c) covering a forming region of the first field effect transistor to form a mask for exposing a forming region of the second field effect transistor and introducing a first impurity into said semiconductor substrate so that a first semiconductor region, which is a semiconductor region for source or drain of said second field effect transistor having a relatively low impurity concentration, is formed self-alignedly relative to the gate electrode of said second field effect transistor;
- and
- (d) forming a side wall insulating film on side walls of the respective gate electrodes of said first and second field effect transistors and introducing a second impurity into said semiconductor substrate so that a second semiconductor region, which is a semiconductor region for source or drain of said second field effect transistor having a relatively high impurity concentration, is formed self-alignedly relative to the gate electrodes and said side wall insulating films of said first and second field effect transistors.
A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:
- forming, on a semiconductor substrate, a plurality of field effect transistors constituting each of a plurality of complementary field effect transistors based SRAM cells and a plurality of field effect transistors forming circuits other than the SRAM cells;
- and
- forming a gate insulating film of at least one first field effect transistor selected among from a plurality of field effect transistors constituting the SRAM cell in a thickness larger than a gate insulating film of a second field effect transistor which is other than said first field effect transistor and is supplied with the same source voltage as said first field effect transistor.
A semiconductor integrated circuit device comprising an SRAM cell having a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, wherein source and drains regions of the n-channel MISFET's and the p-channel MISFET's are formed within a semiconductor substrate such that a drain region of the first n-channel MISFET, a drain region of the first p-channel MISFET, a gate electrode of the second n-channel MISFET, and a gate electrode of the second p-channel MISFET are electrically connected with one another, and a drain region of the first n-channel MISFET, a drain region of the first p-channel MISFET, a gate electrode of the second n-channel MISFET, and a gate electrode of the second p-channel MISFET are electrically connected with one another, at least one of the n-channel MISFET and the p-channel MISFET having an offset structure established between the drain region and the gate electrode thereof.
A semiconductor integrated circuit device comprising an SRAM cell having a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, wherein source and drains regions of the n-channel MISFET's and the p-channel MISFET's are formed within a semiconductor substrate such that a drain region of the first n-channel MISFET, a drain region of the first p-channel MISFET, a gate electrode of the second n-channel MISFET, and a gate electrode of the second p-channel MISFET are electrically connected with one another, and a drain region of the first n-channel MISFET, a drain region of the first p-channel MISFET, a gate electrode of the second n-channel MISFET, and a gate electrode of the second p-channel MISFET are electrically connected with one another, at least one of the n-channel MISFET and the p-channel MISFET being arranged such that the drain region thereof is distant in a direction of being kept away from an end portion of the gate electrode.
A semiconductor integrated circuit device comprising an SRAM cell and a peripheral circuit, said SRAM having a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, wherein source and drains regions of the n-channel MISFET's and the p-channel MISFET's are formed within a semiconductor substrate such that a drain region of the first n-channel MISFET, a drain region of the first p-channel MISFET, a gate electrode of the second n-channel MISFET, and a gate electrode of the second p-channel MISFET are electrically connected with one another, and a drain region of the first n-channel MISFET, a drain region of the first p-channel MISFET, a gate electrode of the second n-channel MISFET, and a gate electrode of the second p-channel MISFET are electrically connected with one another, said peripheral circuit including an n-channel MISFET and a p-channel MISFET, wherein an impurity concentration at a portion contacting the channel region of the drain region of the p-channel MISFET of the SRAM cell is lower than an impurity concentration at a portion contacting the channel region of the drain region of the p-channel MISFET of said peripheral circuit.
A semiconductor integrated circuit device comprising an SRAM cell and a peripheral circuit, said SRAM having a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, wherein source and drains regions of the n-channel MISFET's and the p-channel MISFET's are formed within a semiconductor substrate such that a drain region of the first n-channel MISFET, a drain region of the first p-channel MISFET, a gate electrode of the second n-channel MISFET, and a gate electrode of the second p-channel MISFET are electrically connected with one another, and a drain region of the first n-channel MISFET, a drain region of the first p-channel MISFET, a gate electrode of the second n-channel MISFET, and a gate electrode of the second p-channel MISFET are electrically connected with one another, said peripheral circuit including an n-channel MISFET and a p-channel MISFET, wherein an impurity concentration at a portion contacting the channel region of the drain region of the n-channel MISFET of the SRAM cell is lower than an impurity concentration at a portion contacting the channel region of the drain region of the n-channel MISFET of said peripheral circuit.
A semiconductor integrated circuit device comprising source and drain regions of each of MISFET's constituting an SRAM cell formed within a semiconductor substrate in such a way that the drain region and a gate electrode are arranged to have an offset structure.
A semiconductor integrated circuit device comprising source and drain regions of each of MISFET's constituting an SRAM cell formed within a semiconductor substrate in such a way that the drain region is arranged to be distant in a direction of being kept away from an end portion of a gate electrode.
A semiconductor integrated circuit device comprising source and drain regions of each of MISFET's constituting an SRAM cell formed within a semiconductor substrate in such a way that an impurity concentration at a portion contacting a channel region of the drain region is lower than an impurity concentration at a portion contacting a channel portion of a drain region of MISFET of a peripheral circuit.
A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:
- (a) forming a gate electrode having a first silicon film formed on a gate insulating film, an SiGe layer formed on the first silicon film and a second silicon film formed on the SiGe film;
- and
- (b) after the step (a), forming a silicide film at least on the second silicon film.
A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:
- (a) depositing a first silicon film on a gate insulating film;
- (b) depositing an SiGe layer on the first silicon film;
- (c) depositing a second silicon film on the SiGe layer;
- (d) pattering the second silicon film, the SiGe layer and the first silicon film to form a gate electrode of a p-channel MISFET and a gate electrode of an n-channel MISFET;
- and
- (e) forming a silicide film at least on the second silicon film.
A semiconductor integrated circuit device comprising:
- a gate electrode including a first silicon film formed on a gate insulating film, an SiGe film formed on the first silicon film, and a second silicon film formed on the SiGe film;
- and
- a silicide film formed at least on the second silicon film.
A semiconductor integrated circuit device comprising:
- gate electrodes of a p-channel MISFET and an n-channel MISFET, each having a first silicon film formed on a gate insulating film, an SiGe film formed on the first silicon film and a second silicon film formed on the SiGe film;
- and
- a silicide film formed at lest on the second silicon film.
Dependencies are inferred from the claim text.