Back to results
US 2002/0001359 A1Published application
Timing circuit with dual phase locked loops
AssigneeZarlink Semiconductor Inc.
InventorsSimon Skierszkan, Robert van der Valk
Life of this patent
Estimating the term…
Abstract
A timing circuit for generating clock signals, includes an acquisition digital phase locked loop with a wide capture range for closely following an input signal with its associated disturbances. An output digital phase locked loop having a slow response relative to the acquisition phase locked loop tracks an output of the acquisition phase locked loop to generate an output signal for the timing circuit.
Claims20
A timing circuit for generating clock signals, comprising:
- an acquisition digital phase locked loop with a wide capture range for closely following an input signal and with its associated disturbances;
- and
- an output digital phase locked loop having a slow response relative to said acquisition phase locked loop, said output digital phase locked loop tracking a digital output of said acquisition phase locked loop to generate an output signal for the timing circuit.
A method of generating clock signals from an input signal subject to errors, comprising:
- tracking the input signal and its error components with an acquisition digital phase locked loop to produce a digital output signal, and
- tracking said digital output signal with an output digital phase locked loop with a slow response relative to said acquisition digital phase locked loop so as to eliminate said error components.
Dependencies are inferred from the claim text.