US 2002/0001254 A1 · Synchronous semiconductor memory device

Abstract

A synchronous semiconductor memory device such as SDRAM easy in timinq adjustment of column selection and capable of reducing cycle time and access time to be minimum value without reducing access margin is provided. The synchronous semiconductor memory device includes a memory cell array constituted in a matrix form, a command decoder and an address buffer operative in synchronism with the leading end of clock signal, a row decoder for decoding row address to select word line of the memory cell, a column control signal generating circuit for generating a column control signal, and a column decoder for taking thereinto column address taken in by the address buffer by a column address taking-in signal generated from the command decoder in synchronism with the leading end of the clock signal to allow a column select signal line to be active.

Claims13

Dependent claims

A synchronous semiconductor memory device comprising:

a memory cell array having memory cells disposed in matrix form and operating on the basis of a clock signal;
a plurality of word lines;
a plurality of column lines;
a row decoder for designating address of the word lines;
a column control signal generating circuit for generating a column control signal;
and
a column decoder for designating address of the column lines
wherein taking-in said column address is performed in synchronism with a leading end of the clock signal and the column control signal is generated in synchromism with a trailing end of the clock signal.

5 more elements

Dependencies are inferred from the claim text.

Synchronous semiconductor memory device

Life of this patent

Synchronous semiconductor memory device

Life of this patent

Abstract

Claims13