US 2002/0001252 A1 · Semiconductor memory device and method of operation having delay pulse generation

Abstract

A semiconductor memory device including a memory core block, a logic circuit and a direct access circuit which control the memory core block, and a delay pulse generation circuit. The logic circuit generates first and second internal clock signals responsive to first and second external clock signals, and operates the memory core block at high speed during a normal operation. The direct access circuit generates first and second internal clock signals responsive to first and second external clock signals, to test the memory core block during a direct access operation. The delay pulse generation circuit generates a pulse signal corresponding to the delay difference between the first and second internal clock signals generated by the direct access circuit. The delay difference is used by a tester to compensate for actual delay of the internal clock signals when the memory core block is tested during the direct access operation.

Claims14

Dependent claims

A semiconductor memory device comprising:

a memory core block including a plurality of memory cells;
a logic circuit that generates a first internal clock signal and a second internal clock signal respectively in response to a first external clock signal and a second external clock signal, and that operates said memory core block at high speed during normal operation;
a direct access circuit that generates a third internal clock signal and a fourth internal clock signal respectively in response to the first external clock signal and the second external clock signal, to test the plurality of memory cells within said memory core block during a direct access operation;
and
a delay pulse generation circuit that generates a pulse signal corresponding to a delay difference between the third internal clock signal and the fourth internal clock signal generated by said direct access circuit.

2 more elements

A method of operating a semiconductor memory device having a memory core block including a plurality of memory cells, comprising:

generating a first internal clock signal and a second internal clock signal respectively responsive to a first external clock signal and a second external clock signal;
operating the memory core block based on the first and second internal clock signals during a normal operation mode;
generating a third internal clock signal and a fourth internal clock signal respectively responsive to the first external clock signal and the second external clock signal;
testing the plurality of memory cells based on the third and fourth internal clock signals during a direct access operation mode;
and
generating a pulse signal corresponding to a delay difference between the third and fourth internal clock signals.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device and method of operation having delay pulse generation

Life of this patent

Semiconductor memory device and method of operation having delay pulse generation

Life of this patent

Abstract

Claims14