Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of sub-word lines each connecting to one row of memory cells, said plurality of sub-word line disposed being aligned in a row direction;
• a main word line provided commonly to said plurality of sub-word lines;
• and
• row selection circuitry driving said main word line and said plurality of sub-word lines to a selected state according to an address signal in a normal operating mode, and driving said main word line and a part of said plurality of sub-word lines to a selected states according to said address signal in a data holding mode for holding storage data in the memory cell.

A semiconductor memory device comprising:

• a plurality of memory sub-blocks, disposed being aligned in a row direction, each having a plurality of normal memory cells arranged in rows and columns;
• a plurality of normal sub-word lines, provided corresponding to the respective rows in each of said memory sub-blocks, and each connecting to normal memory cells on a corresponding row;
• a plurality of normal main word lines, disposed extending in the row direction in common to said plurality of memory sub-blocks, each provided corresponding to a prescribed number of normal sub-word lines in each of said plurality of memory sub-blocks;
• a plurality of spare memory cells, disposed being aligned on at least one row in each of said plurality of memory sub-blocks, being disposed in alignment in a column direction with the normal memory cells in a corresponding memory sub-block;
• a plurality of spare sub-word lines, provided corresponding to rows of the spare memory cells in each of said plurality of memory sub-blocks, each connecting to spare memory cells on a corresponding row;
• at least one spare main word line, disposed extending in the row direction in common to the plurality of memory sub-blocks, provided corresponding to a prescribed number of spare sub-word lines in each of said plurality of memory sub-blocks;
• and
• a repairing control circuit storing a defect address indicating a position of a defective normal memory cell, for replacing a normal sub-word line provided corresponding to a row including said defective normal memory cell with a spare sub-word line in a corresponding memory sub-block when said defective normal memory cell is addressed, said repairing control circuit performing replacement for defect repairing with a memory block being a unit at least in a data holding mode.

A semiconductor memory device comprising:

• a memory array having a plurality of memory cells disposed in rows and columns;
• a circuit for storing bit information indicating a storage capacity of said memory array;
• and
• a refresh size setting circuit for setting a size of rows to be refreshed in the memory array based on said bit information in a refresh mode for refreshing storage data in said memory array.