Semiconductor memory device permitting improved integration density and reduced accessing time

A semiconductor memory device, comprising:

• a first plurality of banks provided in the column-direction, each said bank including a second plurality of memory cell blocks provided in the row-direction, each said memory cell block having a plurality of memory cells arranged in a matrix of rows and columns and bit line pairs provided corresponding to the memory cell columns;
• a row selecting circuit responsive to an address signal for selecting a corresponding bank and a corresponding memory cell row;
• a column selecting circuit responsive to said address signal for generating a column selecting signal to select a corresponding memory cell column;
• a plurality of first column selecting lines provided in common to said first plurality of banks in the column-direction for transmitting said column selecting signal;
• a plurality of first input/output line pairs provided corresponding to said first plurality of banks in the row-direction;
• and
• a first selecting circuit for transmitting data read out from a memory cell column selected in response to said column selecting signal to said first input/output line pair,
• each said first selecting circuit including,
• a plurality of first gate circuits provided corresponding to memory cell columns in said memory cell block and controlled by a corresponding one of said first column selecting lines,
• each said first gate circuit including,
• a first transfer gate circuit provided on a transmission path between a bit line pair for a corresponding memory cell and one of said first input/output line pairs and controlled by said corresponding first column selecting line to switch between conductive and disconnected states, and
• a direct sense type gate circuit provided in series with the first transfer gate circuit on said transmission path.

A semiconductor memory device, comprising:

• a first plurality of banks provided in the column-direction,
• each said bank including a second plurality of memory cell blocks provided in the row-direction,
• each said memory cell block including a plurality of memory cells arranged in a matrix of rows and columns and bit line pairs provided corresponding memory cell columns;
• a row selecting circuit responsive to an address signal for generating a bank selecting signal to select a corresponding bank and selecting a memory cell row;
• a plurality of bank selecting lines provided in the row-direction for each of said banks for transmitting said bank selecting signal;
• a column selecting circuit responsive to said address signal for generating a column selecting signal to select a corresponding memory cell column;
• a plurality of column selecting lines provided in common to said first plurality of banks in the column-direction for transmitting said column selecting signal;
• a plurality of input/output line pairs provided in the row-direction corresponding to said first plurality of banks;
• and
• a selecting circuit for transmitting data read out from a memory cell column selected in response to said column selecting signal to said input/output line pair,
• each said selecting circuit including a plurality of gate circuits provided corresponding to said memory cell blocks and each controlled by a corresponding one of said column selecting lines,
• each said gate circuit including,
• a product signal generating circuit responsive to said activation of a corresponding column selecting line and a corresponding bank selecting signal for generating an active driving signal;
• and
• a transfer gate circuit provided on a transmission path between a bit line pair for a corresponding memory cell column and one of said input/output line pairs and controlled by said driving signal to attain a conductive or disconnected state.