Semiconductor memory device for providing address access time and data access time at a high speed

A semiconductor memory device comprising:

• a clock control unit for receiving a delay locked loop (DLL) disable signal, a DLL reset signal, a power-up signal, a self-refresh request signal and a self-refresh signal to generate a DLL control signal and a clock selection signal;
• a clock generation unit for receiving an external clock and the power-up signal to generate an internal clock;
• a DLL clock buffer unit for generating a DLL clock using the external clock;
• a column address strobe (CAS) buffer unit for receiving and buffering the DLL control signal, an external CAS signal and a reference voltage signal to generate an internal CAS signal and an inverted internal CAS signal;
• and
• a CAS latch unit for receiving and latching the internal CAS signal, the inverted internal CAS signal, the internal clock, the DLL clock, the DLL control signal, the external CAS signal and the reference voltage signal to generate a final CAS signal and an inverted final CAS signal.

A method of propagating a signal through a semiconductor memory device, comprising the steps of:

• providing an external clock;
• buffering the external clock;
• generating a delay locked loop (DLL) clock in substantial synchronization with the external clock;
• and
• providing the DLL clock to a control signal buffer and an address buffer.