Semiconductor integrated circuit device using substrate bising and device control method thereof
OwnerTetsuya Fujita, Tadahiro Kurodainventors
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Abstract
A back gate of a P-channel MOS transistor constituting a CMOS input protection circuit or a CMOS output protection circuit, is biased by a voltage higher than a peak voltage of overshoot of an input signal or an output signal, or a back gate of an N-channel MOS transistor constituting an input protection circuit or an output protection circuit, is biased by a voltage lower than a negative peak voltage of undershoot, thereby restricting a current inflow to a substrate from an I/O terminal that might cause a latch-up in the CMOS semiconductor integrated circuit.
Claims14
A semiconductor integrated circuit device comprising:
- a CMOS-based input protection circuit or a CMOS-based output protection circuit constructed of a pair of a P-channel MOS transistor and an N-channel MOS transistor,
- wherein a back gate of said P-channel MOS transistor is biased at a voltage higher than a peak voltage of an overshooting input or output signal of said P-channel MOS transistor, or a back gate of said N-channel MOS transistor is biased at a voltage lower than a negative peak voltage of undershooting input or output signal of said N-channel MOS transistor.
A method of controlling a semiconductor integrated circuit device having a CMOS-based input protection circuit or a CMOS-based output protection circuit constructed of a pair of a P-channel MOS transistor and an N-channel MOS transistor, said method comprising:
- a step of biasing a back gate of said P-channel MOS transistor at a voltage higher than a peak voltage of an overshooting of an input signal or an output signal of said P-channel MOS transistor, or biasing a back gate of said N-channel MOS transistor at a voltage lower than a negative peak voltage of an undershooting of the input signal or the output signal.
Dependencies are inferred from the claim text.