Adiabatic charging register circuit
AssigneeNippon Telegraph and Telephone Corporation
InventorsShunji Nakata, Yuuichi Kado
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Abstract
An adiabatic charging register circuit comprising a plurality of n-channel MOSFET's and a plurality of p-channel MOSFET's, is operated by a clock signal which has a gradually rising and a gradually falling waveform generated by using a charge recycle power source in which charge supplied to a load is at least partially collected to said charge recycle power source, and following inequality is satisfied; |VTN|+|VTP|≧VDD where VTN is threshold of an n-channel MOSFET, VTP is threshold of a p-channel MOSFET, and VDD is output voltage of said charge recycle power source.
Claims5
A register circuit having a plurality of n-channel MOSFET transistors and a plurality of p-channel MOSFET transistors, accepting an input data, and a clock signal, and providing an output data,
- said clock signal being a power clock signal having a gradually rising and gradually falling waveform generated by using a charge recycle power source in which power supplied to a load is at least partially collected to said charge recycle power source, and
- following inequality is satisfied;
- |VTN|+|VTP|≧VDD
- where VTN is threshold of said n-channel MOSFET transistor, VTP is threshold of said p-channel MOSFET, and VDD is output voltage of said charge recycle power source.
Dependencies are inferred from the claim text.