Delay locked loop with reduced noise response

A delay locked loop for use in a semiconductor memory device, the delay locked loop comprising:

• a delay modeling circuit;
• a first clock buffer for receiving an external clock signal and for producing a falling clock signal activated at a falling edge of the external clock signal;
• a second clock buffer for receiving the external clock signal and for producing a rising clock signal activated at a rising edge of the external clock signal;
• a clock divider for producing a reference signal at predetermined clocks of the rising clock signal;
• a phase comparator for comparing the reference signal from the clock divider with a feedback signal from the delay modeling circuit;
• a first low pass filter for producing a first shift signal;
• a second low pass filter for producing a second shift signal;
• a shift controller in communication with the phase comparator and the first and second low pass filters, the shift controller being adapted to selectively produce a right shift signal and a left shift signal;
• a shift register responsive for controlling delay amount to the right shift signal and the left shift signal from the shift controller;
• a first delay line responsive to an output signal of the shift register for adjusting a delay amount of an output signal of the clock divider;
• a second delay line responsive to the output signal of the shift register for adjusting a delay amount of the rising clock signal;
• a third delay line responsive to the output signal of the shift register for adjusting a delay amount of the falling clock signal;
• a delay locked loop signal driving circuit for driving internal circuitry with outputs of the second and third delay lines;
• a low pass filter controlling circuit for receiving a delay locked loop locking signal, from the shift controller to generate a low pass filter activating signal,
• wherein the first low pass filter is responsive to the low pass filter activating signal from the low pass filter controlling circuit and to a first comparator signal output by the phase comparator to output the first shift signal if the first phase comparison signal is identical for a predetermined number of times sequentially, and
• wherein the second low pass filter is responsive to the low pass filter activating signal from the low pass filter controlling circuit and to a second comparator signal output by the phase comparator to output the second shift signal if the second phase comparison signal is identical for a predetermined number of times sequentially and wherein the delay modeling circuit compensator time difference between the external clock signal and an internal clock signal by using a delay adjusted feedback delay signal received from the first delay line.