Sense amplifier circuit
AssigneeNEC Corporation
InventorTatsuya Matano
Life of this patent
Estimating the term…
Abstract
A sense amplifier circuit including a current difference amplification circuit and a voltage difference amplification circuit, and a precharge circuit for precharging digit lines, are provided between the digit lines. A memory cell including one transistor and one capacitor is connected to the digit line. The voltage difference amplification circuit includes an n-channel flip flop and a p-channel flip flop, and is provided with nodes. The nodes are connected to the digit lines via a sense amplifier connection circuit.
Claims15
A sense amplifier circuit for amplifying a signal difference between complementary data lines of a semiconductor memory device, comprising:
- a converting unit which converts a difference between respective currents flowing along the complementary data lines into a voltage difference;
- and
- an amplifying unit which amplifies the voltage difference to a logic level so as to write the logic level back to the complementary data lines.
A sense amplifier circuit for amplifying a signal difference between complementary data lines of a semiconductor memory device, comprising:
- a current difference amplification circuit for amplifying a potential difference between the complementary data lines by using a difference between respective currents flowing into the complementary data lines which occurs due to the potential difference between the complementary data lines;
- a pair of nodes connected to the current difference amplification circuit for outputting the amplified potential difference;
- a voltage difference amplification circuit connected to the nodes for amplifying the potential difference between the nodes into a logic level;
- a precharge circuit connected to the nodes for causing a current to flow from the current difference amplification circuit to the complementary data lines;
- and
- a sense amplifier connection circuit connected to the nodes and the complementary data lines for electrically connecting or disconnecting the nodes to or from the complementary data lines.
Dependencies are inferred from the claim text.