Logic gate cell
AssigneeAIL Corporation
InventorKAZUO TAKI
Life of this patent
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Abstract
To provide a small-area and low-power-consuming logic gate cell which is constructed of a circuit of two inverting logic gates connected in series in a layout of four-step diffusion regions. A first inverting logic gate is formed of a small transistor on internal two-step diffusion regions, a second inverting logic gate is formed of external two-step diffusion regions, and output wirings of the second inverting logic gate is formed of second metal layer wirings so that the second metal layer wirings extend over the first inverting logic gate.
Claims48
A logic gate cell used as an element in an LSI manufactured through CMOS process, having a circuit arrangement composed of two inverting logic gates (1, 2) with the output of a first inverting logic gate (1) connected to one of inputs of a second inverting logic gate (2), and having a single well (19) for forming a P-type MOS transistor in a cell layout, with the well (19) arranged in the top portion of a drawing of the cell layout,
- wherein the logic gate cell is firstly characterized in that the logic gate cell comprises a first diffusion region (11) and a second diffusion region (12) within the well (19), for forming a P-type MOS transistor, with the second diffusion region (12) arranged below the first diffusion region (11), and a third diffusion region (13) and a fourth diffusion region (14), outside and below the well (19), for forming an N-type MOS transistor, with the fourth diffusion region (14) arranged below the third diffusion (13),
- secondly characterized in that the first inverting logic gate (1) is formed of the second diffusion region (12) and the third diffusion region (13), and in that the second inverting logic gate (2) is formed of the first diffusion region (11) and the fourth diffusion region (14), and
- thirdly characterized in that a wiring (37), which also serves as the wiring of an output portion of the second inverting logic gate (2), for interconnecting the P-type MOS transistor and the N-type MOS transistor, is partly or entirely formed of a second metal layer wiring (9), and in that the second metal layer wiring (9) extends over the second diffusion region (12) and the third diffusion region (13).
A logic gate cell used as an element in an LSI manufactured through CMOS process, having a circuit arrangement composed of two inverting logic gates (1, 2) with the output of a first inverting logic gate (1) connected to one of inputs of a second inverting logic gate (2), and having a first diffusion region (11) and a second diffusion region (12) for forming a P-type MOS transistor and a third diffusion region (13) and a fourth diffusion region (14) for forming a N-type MOS transistor in a cell layout,
- wherein the logic cell is firstly characterized in that, when the diffusion regions (11,12) for forming the P-type MOS transistor are arranged in a top portion of a drawing of the cell layout, the second diffusion region (12) is arranged below the first diffusion region (11), the third diffusion region (13) is arranged below the second diffusion region (12) and the fourth diffusion region (14) is arranged below the third diffusion region (12),
- secondly characterized in that the inverting logic gate (1) is formed of the second diffusion region (12) and the third diffusion region (13), and in that the second inverting logic gate (2) is formed of the first diffusion region (11) and the fourth diffusion region (14), and
- thirdly characterized in that a wiring (37), which also serves as the wiring of an output portion of the second inverting logic gate (2), for interconnecting the P-type MOS transistor and the N-type MOS transistor, is partly or entirely formed of a second metal layer wiring (9), and in that the second metal layer wiring (9) extends over the second diffusion region (12) and the third diffusion region (13).
Dependencies are inferred from the claim text.