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US 2002/0000826 A1Published application
Semiconductor parametric testing apparatus
AssigneeAgilent Technologies, Inc.
InventorTakayuki Takao
Life of this patent
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Abstract
The present invention makes it easier to find defective spots on wafers, to test them in more detail, and investigate their causes. A semiconductor parametric testing apparatus is provided that includes means for designating a die 107, 20 and module 106, 21 on each wafer at which a test should be paused and that pauses a test at a preselected die and module on each wafer 104, 2.
Claims9
A semiconductor parametric testing apparatus which allows an operator to designate a die and/or module on each wafer at which a test should be paused.
A semiconductor parametric testing apparatus comprising:
- display means for displaying a map for dices and/or modules on a wafer;
- pointer means for pointing a particular die and/or module on the map;
- marking means for setting a break point at which a test is to be paused using the pointer means;
- a memory for storing the position of the break point marked by using the marking means;
- and
- means for stopping a test at the breakpoint.
3 more elements
Dependencies are inferred from the claim text.