Tester for a semiconductor ic circuit having multiple pins

Abstract

The present invention relates to a tester for testing a semiconductor IC circuit having multiple pins, comprising a timing signal generator, a test signal generator for outputting a test signal to an input pin of a semiconductor IC circuit. The tester in the prior art has the drawbacks that the size of the circuit of the tester increases according to the number of input/output pins of a semiconductor IC circuit, because the timing signal generator, the test signal generator, etc have to be prepared for each of the input pins of a semiconductor IC circuit. As a result, the production cost of a tester increases, according to the number of the input pins of a semiconductor IC circuit. A tester is proposed, in which the timing signal generating means can supply timing signals to all the test signal generating means or to one or some of the test signal generating means.

Dependencies are inferred from the claim text.