US 2002/0000668 A1Published application

Semiconductor device

AssigneeKabushiki Kaisha Toshiba

InventorsKazuhisa Sakihama, Akira Yamaguchi

Life of this patent

Estimating the term…

Loading patent…

Abstract

Provided is a bonding pad structure of a semiconductor device that is unlikely to give rise to an open failure caused by the electromigration in the pad wiring portion. The input-output signal current and the power supply current of the semiconductor chip flowing through the bonding wire is branched to flow from the bonding region into the underlying metal wiring through via metals. A via metal connecting region consisting of the underlying metal wiring layer is formed in the lower peripheral region of the bonding region so as to allow the current flowing from the bonding wire to be branched from the upper via metal connecting region formed in the bonding pad region into the underlying metal wiring connected to the underlying via metal connecting region through a plurality of via metals so as to moderate the current concentration and, thus, to avoid the open failure caused by the electromigration.

Claims16

Dependent claims

A semiconductor device, comprising:

a plurality of metal wiring layers laminated one upon the other on a semiconductor chip with an interlayer insulating film interposed therebetween;
a bonding pad portion formed on an upper metal wiring layer in said plural metal wiring layers;
a passivation film formed to cover the bonding pad portion;
a pad open portion formed in the passivation film;
and
an underlying pad structure in at least one layer of the underlying metal wiring layer included in the plural metal wiring layers;
wherein the bonding pad portion includes a bonding region covering the bottom surface of the pad open portion, an extension region extending from the bottom surface of the pad open portion to the outside of the bonding region, and an upper via metal connecting region formed on the outside of the extension region along at least one side of the extension region;
the underlying pad structure includes an underlying via metal connecting region formed to surround the bonding region;
the upper via metal connecting region is connected to the underlying via metal connecting region through a plurality of via metals formed through the interlayer insulating film positioned adjacent to the lower portion of the upper metal wiring layer;
and
where a plurality of underlying wiring layers are present, said underlying via metal connecting regions formed respectively in the underlying wiring layers positioned adjacent to each other with an interlayer insulating film interposed therebetween are connected to each other through a plurality of via metals formed through said interlayer insulating films.

8 more elements

A semiconductor device, comprising:

a plurality of metal wiring layers laminated one upon the other on a semiconductor chip with an interlayer insulating film interposed therebetween;
a bonding pad portion formed on the upper metal wiring layer included in said plural metal wiring layers;
a passivation film formed to cover said bonding pad portion;
a pad open portion formed in said passivation film;
and
an underlying pad structure formed in at least one underlying metal wiring layer included in said plural metal wiring layers;
wherein said bonding pad portion includes:
a bonding region covering the bottom surface of said pad open portion;
an extension region extending from the bottom surface of said pad open portion to the outside of said bonding region;
and
an upper via metal connecting region formed on the outside of said extension region along at least one side of said extension region;
said underlying pad structure includes an underlying region covering a region right under said bonding region, and an underlying via metal connecting region extending from said underlying region in a manner to surround the outside of said underlying region;
said upper via metal connecting region is connected to said underlying via metal connecting region through a plurality of via metals formed through an interlayer insulating film positioned adjacent to the lower portion of said upper metal wiring layer;
and
where a plurality of underlying wiring layers are present, said underlying via metal connecting regions formed respectively in the underlying wiring layers positioned adjacent to each other with an interlayer insulating film interposed therebetween are connected to each other through a plurality of via metals formed through said interlayer insulating film.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/896,073Filed 28 Jun 2001
Priority: JP 2000-19589929 Jun 2000
Published: 3 Jan 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10W 72/90
Interconnections or connectors in packages: bond pads, in general
H10W 72/50
Interconnections or connectors in packages: bond wires
H10W 70/60
Package substrates; Interposers; Redistribution layers [RDL]: insulating or insulated package substrates; Interposers; Redistribution layers
H10W 72/075
Connecting or disconnecting: of bond wires

Family

US 6,522,021 B2Related patent
US 2002/0000668 A1This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key