Method of forming an integrated circuit contact structure having gate electrode protection for self-aligned contacts with zero enclosure
AssigneeSTMicroelectronics S.r.l.
InventorLOI N. NGUYEN
Life of this patent
Estimating the term…
Abstract
A technique for forming integrated circuit device contacts includes the formation of nitride spacers along side gate electrodes for LDD definition. In addition, a nitride cap layer is formed over the gate electrodes. When a contact opening is formed through the interlevel oxide dielectric, the nitride cap and sidewall spacers protect the gate electrode from damage and shorting. A highly doped poly plug is formed in the opening to make contact to the underlying substrate. Metalization is formed over the poly plug in the usual manner.
Claims25
A method for forming a contact in an integrated circuit device, comprising the steps of:
- forming a gate electrode on a substrate surface, the gate electrode having a top layer of a first material;
- forming sidewalls alongside the gate electrode of the first material;
- forming an interlevel dielectric layer over the gate electrode, sidewalls, and substrate, wherein the interlevel dielectric can be selectively etched over the first material;
- etching an opening through the interlevel dielectric layer to expose a portion of the substrate, wherein the gate electrode is protected by the sidewalls and top cap;
- forming a conductive plug in the opening;
- and
- forming a layer of interconnect over the interlevel dielectric and the conductive plug.
A contact structure for an integrated circuit device, comprising:
- a substrate having a surface;
- a gate electrode on the substrate surface, wherein the gate electrode has a cap layer of a first material;
- a sidewall of the first material alongside the gate electrode;
- a interlevel dielectric layer of a second material on the gate electrode and the substrate surface, the interlevel dielectric layer having an opening therethrough to expose a portion of the substrate surface adjacent the sidewall, wherein a portion of the sidewall is also exposed in the opening;
- a conductive plug in the opening in contact with the substrate surface and the exposed portion of the sidewall;
- and
- an interconnect layer on the interlevel dielectric layer and the conductive plug.
Dependencies are inferred from the claim text.