Method to fabricate a floating gate with a sloping sidewall for a flash memory

A method for fabrication of stacked gate structure for a Flash EEPROM cell:

• providing a semiconductor substrate;
• providing field oxide isolation regions in said substrate;
• providing a tunneling oxide layer overlying said isolation regions and said substrate;
• depositing a first polysilicon layer overlying said tunneling oxide layer;
• forming a photoresist mask overlying said first polysilicon layer;
• isotropically etching away said first polysilicon layer and said tunneling oxide layer in areas not covered by said photoresist mask to create said floating gates with outwardly sloping sidewall edges;
• etching away said photoresist layer;
• depositing an interpoly dielectric layer overlying said floating gates, said sloping sidewall edges, and said isolation regions;
• depositing a second polysilicon layer overlying said interpoly dielectric;
• and
• completing said fabrication of stacked gate structures in said Flash EEPROM cells.

A stacked gate for a Flash EEPROM device comprising:

• field oxide isolation regions on and in a semiconductor substrate to isolate the active device area;
• a tunneling oxide layer overlying said semiconductor substrate;
• a first polysilicon layer overlying said tunneling oxide layer wherein said polysilicon layer and said tunneling oxide form a floating gate and wherein the sidewall edges of said floating gate are outwardly sloped;
• an interpoly dielectric layer overlying said floating gate;
• and
• a second polysilicon layer overlying said interpoly dielectric layer wherein said second polysilicon layer forms a control gate overlying said floating gate completing the stacked gate for a Flash EEPROM device.