Semiconductor integrated circuit device and process for manufacturing the same
AssigneeHitachi, Ltd.
InventorsKiyonori Ohyu, Makoto Ohkura, Aritoshi Sugimoto, Yoshitaka Tadaki, Makoto Ogasawara, Masashi Horiguchi, Norio Hasegawa, Shinichi Fukada
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Abstract
A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.
Claims18
A semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells and a plurality of relief cells formed in a memory array,
- wherein the element isolation width of the region having said relief cells is made larger than that of the region having said memory cells.
A semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells and a plurality of relief cells formed in a memory array,
- wherein the width of the active region having said relief cells is larger than the active-region having said memory cells.
A semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells and a plurality of relief cells formed in a memory array,
- wherein the element isolation width of the region having said relief cells is larger than that of the region having said memory cells, and
- wherein the width of the active region having said relief cells is larger than the active-region having said memory cells.
A semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells and a plurality of relief cells formed in a memory array,
- wherein side wall spacers formed on the side walls of the gate electrode of the MISFET included in each of said relief cells are thicker than side wall spacers formed on the side walls of the gate electrode of the MISFET included in each of said memory cells.
A semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells and a plurality of relief cells formed in a memory array,
- wherein a gate insulating film of the MISFET included in each of said relief cells is thicker than a gate oxide film of the MISFET included in each of said memory cells.
A semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells and a plurality of relief cells formed in a memory array,
- wherein the number of said relief cells to be connected with one redundant bit line is smaller than that of said memory cells to be connected with one bit line.
A semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells formed in a memory array and including relief cells,
- wherein a sense amplifier to be used for relief is connected with a first bit line or a signal line of the information of a noted bit and a second bit line or a signal line of the opposit information of said noted bit, and
- wherein one of two cells to be selected by a predetermined word line is connected with said first bit line whereas the other cell is connected with said second bit line.
A semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells formed in a memory array and including relief cells,
- wherein a sense amplifier to be used for relief is connected with a first bit line or a signal line of the information of a noted bit and a second bit line or a signal line of the opposit information-of said noted bit, and
- wherein one of two word lines to be simultaneously selected selects the cell connected with said first bit line whereas the other selects the cell connected with said second bit line.
A semiconductor integrated circuit device comprising a DRAM having a plurality of memory cells formed in a memory array and including relief cells,
- wherein a sense amplifier to be used for a relief is connected with two first bit lines or signal lines of the information of a noted bit and two second bit lines or signal lines of the opposit information of said noted bit, and
- wherein one of two word lines to be simultaneously selected selects the cell connected with one of said two first bit lines whereas the other selects the cell connected with one of said two second bit lines.
A process for manufacturing a DRAM having a plurality of normal cells and a plurality of relief cells formed in a memory array, comprising:
- (a) thermally treating a semiconductor substrate to form a first gate insulating film on the surface thereof and then selectively removing said first gate insulating film of the normal cell region;
- (b) thermally treating said semiconductor substrate again to form a second gate insulating film in said normal cell region, and making said first gate insulating film in the relief cell region thicker than said second gate insulating film;
- (c) forming gate electrodes of the normal cells over the second gate insulating film of said normal cell region and gate electrodes of the relief cells over the first gate insulating film of said relief cell region by patterning the first conductive film deposited on said semiconductor substrate;
- (d) forming sources and drains of the normal cells over said semiconductor substrate in said normal cell region and sources and drains of the relief cells over said semiconductor substrate in said relief cell region;
- (e) forming first side wall spacers on the side walls of said gate electrodes in said normal cell region by depositing a first insulating film on said semiconductor substrate, and by etching said first insulating film in said normal cell region selectively;
- (f) forming second side wall spacers thicker than said first side wall spacers on the side walls of said gate electrodes in said relief cell region by depositing a second insulating film on said semiconductor substrate, and by etching said second insulating film;
- (g) forming contact holes individually over either the sources or drains of said normal cells and over either the sources or drains of said relief cells by etching a third insulating film deposited on the semiconductor substrate;
- and
- (h) forming capacitive elements for storing the information stored in said normal cells and capacitive elements for storing the information stored in said relief cells individually over said third insulating film.
Dependencies are inferred from the claim text.