Semiconductor memory of good retention and its manufacture

A method of manufacturing a semiconductor device, comprising the steps of:

• forming an element isolation insulating film in a principal surface of a first conductive type area of a semiconductor substrate, the element isolation insulating film defining an active region;
• selectively introducing impurities of a second conductivity type opposite to the first conductivity type into end portions of the active region to form first impurity doped regions;
• forming a gate insulating film on the active region;
• forming a word line made of conductive material on the gate insulating film, a pattern of the word line not overlapping the first impurity doped region, traversing the active region, and extending in one direction as a whole;
• introducing impurities of the second conductivity type into the active region by using the word line and the element isolation insulating film as a mask, to form second impurity doped regions at least partially overlapping the first impurity doped regions;
• and
• forming a capacitor connected to one of the second impurity doped regions and extending over the word line.

A semiconductor device comprising:

• a semiconductor substrate having one principal surface and a first conductivity type surface area exposed to the principal surface;
• an element isolation insulating region formed in the principal surface of said semiconductor device and defining a plurality of active regions in the first conductivity type surface area;
• a gate insulating film formed on a surface of each of the plurality of active regions;
• a plurality of word lines each partially disposed on said gate insulating film on the principal surface and made of conductive material, each of the plurality of word lines extending in a first direction as a whole and having a concave area near an adjacent active region;
• a plurality of bit lines extending in a second direction as a whole, intersecting with the first direction on the principal surface;
• a plurality of capacitors formed on the principal surface;
• and
• a plurality of memory cell transistors formed in the plurality of active regions, each memory cell using one word line as a gate electrode and having a pair of source and drain regions of a second conductivity type opposite to the first conductivity type, the source and drain regions being defined by the gate electrode and said element isolation insulating region, one of the pair of source and drain regions being connected to one of the plurality of bit lines, the other of the pair of source and drain regions being connected to one of the plurality of capacitors, three sides of an area of the other of the pair of source and drain regions being defined by said element isolation insulating region and facing the concave area of another word line adjacent to the word line.