Semiconductor integrated circuit device including semiconductor memory with tester circuit capable of analyzing redundancy repair

A semiconductor integrated circuit device comprising:

• a memory cell array having a plurality of memory cells arranged in a matrix, each retaining stored data, said memory cell array being divided into a plurality of sub memory cell arrays,
• each said sub memory cell array including p1 a normal memory cell array including a plurality of normal memory cells, and
• a spare memory cell array including a plurality of spare memory cells;
• a memory cell select circuit to select a plurality of said memory cells at once for each said sub memory cell array according to an address signal;
• a data transmission circuit to transfer said stored data with respect to a selected said memory cell;
• and
• a plurality of tester circuits provided for each said sub memory cell array, detecting a defective memory cell in said normal memory cell array and determining which said spare memory cell is to be used for replacement,
• each said tester circuit including
• a defective address detection circuit controlling said memory cell select circuit to sequentially select said memory cell while writing test data in a test write operation, and detecting a defective address corresponding to a defective memory cell according to a comparison result between data read out from said memory cell and expected value data in a test readout operation,
• an address storage circuit to store said defective address, and
• a determination circuit determining which of said spare memory cell is to be used for replacement according to said defective address retained in said address storage circuit,
• said address storage circuit selectively storing a defective address differing from a defective address already stored out of sequentially detected defective addresses under control of said determination circuit.