Latch structure for interlocked pipelined CMOS (IPCMOS) circuits

A method for transferring data in an interlocked pipeline circuit having a plurality of stages, comprising the steps of:

• providing, for each stage, a latch connected to an input of that stage and a switch for selectively coupling the input of the stage to an output of the previous stage;
• when the data is valid in a current stage, sending a valid signal to a local clock circuit of a next stage of the plurality of stages;
• sending an acknowledge signal from the local clock circuit of the next stage to a local clock circuit of the current stage responsive to the valid signal;
• generating a local clock signal at the local clock circuit of the current stage of the plurality of stages based on the acknowledge signal and the valid signal;
• and
• enabling the switch of the current stage based on the local clock signal to permit data transfer to the latch of the current stage from the output of the previous stage.