Back to results
US 2001/0056455 A1Published application
Family of low power, regularly structured multipliers and matrix multipliers
OwnerRong Lininventor
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
OwnerRong Lininventor
Estimating the term…
A family of embodiments of a new class of CMOS VLSI computer multiplier circuits that are simpler to fabricate, smaller, faster, more efficient in their use of power, and easier to scale in size than the prior art. The normal binary adder circuit unit is replaced by the innovative shift switch circuit unit. Use of the shift switch circuit sharply reduces fluctuations of power caused by plurality variations in the bit representations of the input, intermediate and output numbers. Reduced-scale devices are used in shift-switch pass-transistor signal restoration circuits, significantly reducing the size, power demand, and power dissipation of internal circuitry, in contrast to ordinary multiplier design. The simplicity of the circuit design allows multiplier partial-product reduction in fewer logic stages than existing comparable designs allow, showing speed improvement over such designs. The circuit design simplicity and the use of reduced-scale devices require less VLSI area than existing designs need, facilitating integration in VLSI microprocessors. Modular circuit organization simplifies scaling for larger operands without the circuit complications of existing designs. The design includes a critical flip of the physical layout of the partial-product matrix at each size level, simplifying the layout of traces in the circuit at all size scales. Finally, the application of reconfigurable design principles to the easily-scaled layout reduces significantly the mean demand for computing resources over a wide range of multiplication bit-width scales, as compared to existing designs. Overall, the orchestrated integration of these diverse design innovations makes possible the implementation of simpler, faster, smaller, more efficient, more flexible, and easier-to-build VLSI multiplication circuits than the current art reveals.
A shift bar circuit for receiving one or more independent binary input signals and converting said binary signals into a state signal having one unique bit and representative of the input binary signals.
A shift switch parallel counter having one bar circuit for receiving one binary input signal of weight 1 and one shift bar binary input signal of weight 1, and producing a binary sum bit of weight 1 and a binary carry bit of weight 2.
A compressor circuit comprising:
A compressor circuit comprising:
A shift switch parallel counter circuit for counting binary input signals and producing a sum signal and a plurality of carry signals, comprising:
A partial product matrix reduction circuit comprising:
The partial product reduction matrix of claim 35 wherein the plurality of interconnected cascaded shift switch parallel counter circuits of the matrix reduction circuits comprises:
The partial product reduction matrix 27 wherein the first, second, and output numbers are floating-point numbers expressed in binary form.
The partial product reduction matrix 29 wherein the first, second, and output numbers are integers expressed in binary form.
The partial product reduction matrix 36 wherein the plurality of interconnected cascaded shift switch parallel counter circuits of the matrix reduction circuits comprises:
A small eight-by-eight shift switch parallel multiplier circuit for multiplying two eight-bit numbers, comprising a plurality of shift switch parallel counters, each shift switch parallel counter further comprising:
A small eight-by-eight shift switch parallel multiplier circuit for multiplying two eight-bit numbers, comprising:
A small shift switch parallel multiplier circuit for multiplying two binary numbers, comprising a plurality of shift switch parallel counters each further comprising a compressor circuit, each said compressor circuit further comprising:
A reconfigurable matrix multiplier circuit for multiplying two mathematical matrices, comprising:
The four matrix multiplier circuits of claim 53 each comprising a set of four identical matrix multiplier circuits, each multiplying two 4-bit numbers.
Dependencies are inferred from the claim text.