Timing control means for automatic compensation of timing uncertainties

A self calibrating receiver comprising:

• a register having a plurality of channels having inputs and outputs;
• a clock means for providing a clock signal to the register;
• a reference signal generator connectable to the input of at least one said channel of said register for supplying reference signals for deskewing the register;
• a detecting means connectable to the output of at least one said channel of said register for detecting a deviation from a predetermined level of probability of reading by said register from said reference channel a desired symbol on a boundary of two reference channel symbols in a sequence;
• wherein the output of the detecting means is connectable to a set of delay means which uses the information received by said detecting means to generate a feedback signal to compensate timing errors in said register.

A self calibrating transmitter with expandable data width, comprising:

• at least one register having at least one channel having an input and output;
• a clock means for providing a clock signal to said register;
• a reference signal generator for supplying reference signals for deskewing said register's channel output in relation to the reference signal;
• a phase comparator, one input of which is connected to the reference signal and another input is connected to a sense signal at the register's output;
• and
• at least one feedback loop associated with the output of said phase comparator, the feedback loop comprising a set of delay means to compensate the timing errors in transmitter channels, wherein
• the reference signal is connectable to the input of the phase comparator;
• and
• an input of at least one said channel of said register is connectable to another signal for providing the sense signal to the phase comparator for deskewing the register.

An integrated circuit incorporating at least one register and a timing control device for the compensation of timing errors to create the characteristics of a zero setup and hold time integrated circuit, wherein

• the timing control device comprises:
• a clock for providing a clock signal;
• a reference signal generator for providing a reference signal applicable through a reference channel to said register, for deskewing the register's channels with respect to said reference signal;
• wherein for each said register a corresponding feedback loop is associated for the relative alignment of register's channels timing in relation to the reference signal, said feedback loop comprising
• a means for detecting a deviation from a predetermined level of probability of reading by said register a desired symbol on a boundary of two reference channel symbols in a sequence of symbols transmitted through the reference channel;
• and
• a set of delay means which uses the determined information on deviation from the predetermined level of said probability to generate a feedback signal to compensate timing errors in said register.

A test system incorporating at least one register and a timing control device for the compensation of timing errors, wherein the timing control device comprises:

• a clock for providing a clock signal;
• a reference signal generator for providing a reference signal applicable through a reference channel to said register, for deskewing the register's channels with respect to said reference signal;
• wherein for each said register a corresponding feedback loop is associated for the relative alignment of register's channels timing in relation to the reference signal, said feedback loop comprising
• a means for detecting a deviation from a predetermined level of probability of reading by said register a desired symbol on a boundary of two reference channel symbols in a sequence of symbols transmitted through the reference channel;
• and
• a set of delay means which uses the determined information on deviation from the predetermined level of said probability to generate a feedback signal to compensate timing errors in said register.

A method for the compensation of timing errors in multiple channel devices comprising at least one register, the method comprising the steps of:

• providing a clock signal to said register;
• providing reference signals for deskewing the register;
• providing reference signals for deskewing the register;
• detecting a deviation from a predetermined level of probability of reading by said register a desired symbol on a boundary of two reference channel symbols in a sequence;
• and
• generating for each said register a feedback signal using the determined information on deviation to compensate timing errors in said register until the clock reaches a zero skew with respect to the reference signal.