Method for fabricating narrow metal interconnects in an integrated circuit using heat and pressure to extrude a metal layer into a lead trench and via/contact

A method for making an integrated circuit, comprising the steps of:

• fabricating on a first planar surface of a base structure a first non-conductive layer having in a side thereof opposite from the base structure a first lead trench which is spaced from the base structure, and having a first via channel which opens at one end into the first lead trench and which opens at the other end through a side of the first nonconductive layer nearest the base structure;
• applying on the side of the first nonconductive layer opposite from the base structure a first liner, the first liner covering exposed surfaces in the first lead trench and the first via channel;
• applying on a side of the first liner opposite from the base structure a first metal layer;
• simultaneously applying heat and pressure so as to cause the first metal layer to be extruded into the first lead trench and the first via channel;
• thereafter carrying out a first planarizing step which creates a substantially planar first surface portion on a side of the first nonconductive layer opposite from the base structure, which removes portions of the first liner and the first metal layer on a side of the first surface portion remote from the base structure, and which creates on a portion of the first metal layer disposed in the first lead trench a second surface portion which is substantially coplanar with the first surface portion;
• fabricating on a second planar surface which includes the first and second surface portions a second nonconductive layer having in a side thereof opposite from the second planar surface a second lead trench which is spaced from the planar surface, and having a second via channel which opens at one end into the second lead trench and which opens at the other end through a side of the second nonconductive layer facing the second planar surface.
• applying on a side of the second nonconductive layer opposite from the second planar surface a second liner, the second liner covering exposed surfaces in the second lead trench and the second via channel;
• applying on a side of the second liner opposite from the second planar surface a second metal layer;
• simultaneously applying heat and pressure so as to cause the second metal layer to be extruded into the second lead trench and the second via channel;
• and
• thereafter carrying out a second planarizing step which creates a substantially planar third surface portion on a side of the second nonconductive layer opposite from the second planar surface, which removes portions of the second liner and the second metal layer on a side of the third surface portion remote from the second planar surface, and which creates on a portion of the second metal layer disposed in the second lead trench a fourth surface portion which is substantially coplanar with the third surface portion.

An integrated circuit, made according to a method which includes the steps of:

• fabricating on a surface of a base structure a nonconductive layer having in a substantially planar side thereof opposite from the base structure a lead trench which is spaced from the base structure, and having a via channel which opens at one end into the lead trench and which opens at the other end through a side of the nonconductive layer nearest the base structure;
• applying on a side of the nonconductive layer opposite from the base structure a liner, the liner covering exposed surfaces in the lead trench and the via channel;
• applying on a side of the liner opposite from the base structure a metal layer;
• simultaneously applying heat and pressure so as to cause the metal layer to be extruded into the lead trench and the via opening;
• and
• thereafter carrying out a planarizing step which creates a substantially planar first surface portion on a side of the nonconductive layer opposite from the base structure, which removes portions of the liner and the metal layer on a side of the first surface portion remote from the base structure, and which creates on a portion of the metal layer disposed in the lead trench a second surface portion which is substantially coplanar with the first surface portion.

A method for making an integrated circuit, comprising the steps of:

• fabricating on a base structure a first non-conductive layer having therethrough a first via channel;
• providing a conductive plug which extends through the first via channel;
• fabricating a metal lead over the first non-conductive layer and the conductive plug, the conductive plug having its upper end electrically coupled to the metal lead;
• filling regions adjacent the metal lead with a non-conductive material;
• carrying out a planarizing step to create on the metal lead and the non-conductive material a substantially planar surface;
• fabricating on the planar surface a second nonconductive layer having in a side thereof opposite from the planar surface a lead trench which is spaced from the planar surface, and having a second via channel which opens at one end into the lead trench and which opens at the other end through a side of the second nonconductive layer facing the planar surface.
• applying on a side of the second nonconductive layer opposite from the planar surface a liner, the liner covering exposed surfaces in the lead trench and the second via channel;
• applying on a side of the liner opposite from the planar surface a metal layer;
• simultaneously applying heat and pressure so as to cause the metal layer to be extruded into the lead trench and the second via channel;
• and
• thereafter carrying out a further planarizing step which creates a substantially planar first surface portion on a side of the second nonconductive layer opposite from the planar surface, which removes portions of the liner and the metal layer on a side of the first surface portion remote from the planar surface, and which creates on a portion of the metal layer disposed in the lead trench a second surface portion which is substantially coplanar with the first surface portion.

A method for making an integrated circuit, comprising the steps of:

• forming a first dielectric layer on a surface of a base structure;
• forming on the first dielectric layer an etch stop layer;
• forming in the etch stop layer an opening;
• forming on the etch stop layer a second dielectric layer;
• and
• etching the first and second dielectric layers so as to create in the second dielectric layer a lead trench and so as to create through the first dielectric layer an opening aligned with the opening through the etch stop layer, the openings through the etch stop layer and the second dielectric layer together defining a via channel.