US 2001/0055349 A1 · Clock recovery circuit

Abstract

In a clock recovery circuit for DTV using a VSB modulation method, if the frequency of the symbol clock is fs, since the frequency difference between the fs/2 component signal of the VSB signal and the pilot signal is constant at fs/2, it is possible accurately to detect the phase error from their differential signal. Furthermore there is no distortion of the clock signal frequency of the VSB signal, even when the symbol data is distorted by multi-pass distortion or the like, since clock signal regeneration is performed by frequency domain processing. By employing this type of principle and performing phase error detection for each symbol at a time, it is possible to ensure a high speed tracking performance for clock signal regeneration.

Claims9

Dependent claims

A clock recovery circuit provided to a receiving device which receives digital broadcasts using a VSB modulation method, comprising:

a first band pass filter which, when a symbol rate of a received signal is fs, extracts a signal of an fs/2 frequency component from an in-phase component of a VSB signal which has been converted to baseband;
a second band pass filter which extracts a signal of an fs/2 frequency component from a quadrature-phase component of said VSB signal;
a delay element which delays an output signal of said second band pass filter by Π/4;
a first multiplier which squares an output signal of said first band pass filter;
a second multiplier which squares an output signal of said delay element;
an adder which adds together an output signal of said first multiplier and an output signal of said second multiplier;
a third band pass filter which extracts a signal of an fs frequency component from an output signal of said adder, and outputs a symbol clock received signal;
a phase error detector which detects a phase error between a symbol clock received signal of said third band pass filter and a reference clock of receiving device;
and
a loop filter which smoothes a phase error signal which is outputted by said phase error detector.

7 more elements

A clock recovery circuit provided to a receiving device which receives digital broadcasts using a VSB modulation method, comprising:

a first band pass filter which, when a symbol rate of a received signal is fs, extracts a signal of an fs/2 frequency component from an in-phase component of a VSB signal which has been converted to baseband;
a second band pass filter which extracts a signal of an fs/2 frequency component from a quadrature-phase component of said VSB signal;
a first low pass filter which extracts a pilot signal from said in-phase component of said VSB signal which has been converted to baseband;
a second low pass filter which extracts a pilot signal from said quadrature-phase component of said VSB signal which has been converted to baseband;
a first complex number arithmetical unit which, when output signals of said first and said second band pass filters are considered as a first complex number signal, and output signals of said first and said low pass filters are considered as a second complex number signal, divides said first complex number signal by said second complex number signal according to the rules for complex number division;
a third band pass filter which extracts a signal of an fs/2 frequency component from an in-phase component of an output signal of said first complex number arithmetical unit;
a fourth band pass filter which extracts a signal of an fs/2 frequency component from a quadrature-phase component of the output signal of said first complex number arithmetical unit;
a second complex number arithmetical unit which, when output signals of said third and said fourth band pass filters are considered as a third complex number signal, squares said third complex number signal;
a first filter which extracts an in-phase component signal which has frequency fs from an output signal of said second complex number arithmetical unit;
a second filter which extracts a quadrature-phase component signal which has frequency fs from the output signal of said second complex number arithmetical unit;
a phase error detector which, when the output signals of said first and said second filters are considered as a fourth complex number signal, detects a phase error between a symbol clock received signal included in said fourth complex number signal and a reference clock of receiving device;
and
a loop filter which smoothes a phase error signal which is outputted by said phase error detector.

10 more elements

A clock recovery circuit provided to a receiving device which receives digital broadcasts using a VSB modulation method, comprising:

a first band pass filter which, when a symbol rate of a received signal is fs, extracts a signal of an fs/2 frequency component from an in-phase component of a VSB signal which has been converted to baseband;
a second band pass filter which extracts a signal of an fs/2 frequency component from a quadrature-phase component of said VSB signal;
a first low pass filter which extracts a pilot signal from said in-phase component of said VSB signal which has been converted to baseband;
a second low pass filter which extracts a pilot signal from said quadrature-phase component of said VSB signal which has been converted to baseband;
a first complex number arithmetical unit which, when the output signals of said first and said second band pass filters are considered as a first complex number signal, and output signals of said first and said low pass filters are considered as a second complex number signal, divides said first complex number signal by said second complex number signal according to rules for complex number division;
a third band pass filter which extracts a signal of the fs/2 frequency component from an in-phase component of an output signal of said first complex number arithmetical unit;
a fourth band pass filter which extracts a signal of the fs/2 frequency component from a quadrature-phase component of said output signal of said first complex number arithmetical unit;
a reference clock of receiving device generator which, with a reference clock of receiving device frequency on a complex number plane being taken as fs′, outputs a reference clock of receiving device having a frequency of fs′/2 as a fourth complex number signal;
a second complex number arithmetical unit which, when output signals of said third and said fourth band pass filters are considered as a third complex number signal, divides said third complex number signal by said fourth complex number signal according to said rules for complex number division;
a third low pass filter which extracts only an in-phase component which has frequency (fs−fs′)/2 from an output signal of said second complex number arithmetical unit;
a fourth low pass filter which extracts only a quadrature-phase component which has frequency (fs−fs′)/2 from the output signal of said second complex number arithmetical unit;
a phase error detector which, when an output signals of said third and fourth low pass filters are considered as a fifth complex number signal, outputs a frequency of said fifth complex number signal as a frequency error of the symbol clock, and outputs a phase of said fifth complex number signal as a phase error of the symbol clock;
and
a loop filter which smoothes a phase error signal which is outputted by said phase error detector.

11 more elements

Dependencies are inferred from the claim text.

Clock recovery circuit

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Clock recovery circuit

Life of this patent

Abstract

Claims9